}
 
 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
-               bool enable)
+                                                    bool enable)
 {
        uint32_t data;
 
-       if (enable) {
+       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
                data = RREG32(mmMC_HUB_MISC_HUB_CG);
                data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
                WREG32(mmMC_HUB_MISC_HUB_CG, data);
 }
 
 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
-               bool enable)
+                                      bool enable)
 {
        uint32_t data;
 
-       if (enable) {
+       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
                data = RREG32(mmMC_HUB_MISC_HUB_CG);
                data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
                WREG32(mmMC_HUB_MISC_HUB_CG, data);
 
                        AMD_CG_SUPPORT_BIF_LS |
                        AMD_CG_SUPPORT_HDP_MGCG |
                        AMD_CG_SUPPORT_HDP_LS |
-                       AMD_CG_SUPPORT_ROM_MGCG;
+                       AMD_CG_SUPPORT_ROM_MGCG |
+                       AMD_CG_SUPPORT_MC_MGCG |
+                       AMD_CG_SUPPORT_MC_LS;
                adev->pg_flags = 0;
                adev->external_rev_id = adev->rev_id + 0x3c;
                break;