*count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 }
 
+static bool cik_need_reset_on_init(struct amdgpu_device *adev)
+{
+       u32 clock_cntl, pc;
+
+       if (adev->flags & AMD_IS_APU)
+               return false;
+
+       /* check if the SMC is already running */
+       clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
+       pc = RREG32_SMC(ixSMC_PC_C);
+       if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
+           (0x20100 <= pc))
+               return true;
+
+       return false;
+}
+
 static const struct amdgpu_asic_funcs cik_asic_funcs =
 {
        .read_disabled_bios = &cik_read_disabled_bios,
        .need_full_reset = &cik_need_full_reset,
        .init_doorbell_index = &legacy_doorbell_index_init,
        .get_pcie_usage = &cik_get_pcie_usage,
+       .need_reset_on_init = &cik_need_reset_on_init,
 };
 
 static int cik_common_early_init(void *handle)