drm/bridge: ti-sn65dsi86: Reject modes with too large blanking

The front and back porch registers are 8 bits, and pulse width registers
are 15 bits, so reject any modes with larger periods.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220831082653.20449-2-tomi.valkeinen@ideasonboard.com

diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index 90bbabde159596761bdc704dc3d61ff419130a84..09d3c65fa2ba73cbe0789a0cda3412c583a1ac1b 100644 (file)
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -747,6 +747,29 @@ ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
        if (mode->clock > 594000)
                return MODE_CLOCK_HIGH;
 
+       /*
+        * The front and back porch registers are 8 bits, and pulse width
+        * registers are 15 bits, so reject any modes with larger periods.
+        */
+
+       if ((mode->hsync_start - mode->hdisplay) > 0xff)
+               return MODE_HBLANK_WIDE;
+
+       if ((mode->vsync_start - mode->vdisplay) > 0xff)
+               return MODE_VBLANK_WIDE;
+
+       if ((mode->hsync_end - mode->hsync_start) > 0x7fff)
+               return MODE_HSYNC_WIDE;
+
+       if ((mode->vsync_end - mode->vsync_start) > 0x7fff)
+               return MODE_VSYNC_WIDE;
+
+       if ((mode->htotal - mode->hsync_end) > 0xff)
+               return MODE_HBLANK_WIDE;
+
+       if ((mode->vtotal - mode->vsync_end) > 0xff)
+               return MODE_VBLANK_WIDE;
+
        return MODE_OK;
 }