*  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
         *  - Disable pll2_pfd2_396m_clk
         */
-       if (of_machine_is_compatible("fsl,imx6ul")) {
+       if (of_machine_is_compatible("fsl,imx6ul") ||
+           of_machine_is_compatible("fsl,imx6ull")) {
                /*
                 * When changing pll1_sw_clk's parent to pll1_sys_clk,
                 * CPU may run at higher than 528MHz, this will lead to
                goto put_clk;
        }
 
-       if (of_machine_is_compatible("fsl,imx6ul")) {
+       if (of_machine_is_compatible("fsl,imx6ul") ||
+           of_machine_is_compatible("fsl,imx6ull")) {
                pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
                secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
                if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) {