ARM: imx6q: use common soc revision helpers

It calls imx_set_soc_revision() to set up soc revision in
imx6q_init_revision(), and replaces all the occurrences of
imx6q_revision() with common helper imx_get_soc_revision().

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 913ad85ad62192648c04b9c1d9e4cc8dbd6bbbd4..c68156621cc88a1654b4b67bfc3c168991a1aad4 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -300,7 +300,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        WARN_ON(!base);
 
        /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
-       if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) {
+       if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
                post_div_table[1].div = 1;
                post_div_table[2].div = 1;
                video_div_table[1].div = 1;
@@ -574,7 +574,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
        clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
 
-       if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) {
+       if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
+           cpu_is_imx6dl()) {
                clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
                clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
        }

diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 6ac25f68a6bc882161a59d018eafe2697cb4a89f..cac12870efb342b7d55d8f42bf85232b6180c0b2 100644 (file)
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -73,7 +73,6 @@ extern void mxc_restart(enum reboot_mode, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
 extern void mxc_arch_reset_init_dt(void);
 extern int mx53_revision(void);
-extern int imx6q_revision(void);
 extern int mx53_display_revision(void);
 extern void imx_set_aips(void __iomem *);
 extern int mxc_device_init(void);

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 3be0fa0e979602580f5cf7639520a61c187cfceb..f260aad9850bebfb2e08341372d22f9979ade857 100644 (file)
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -38,16 +38,10 @@
 #include "cpuidle.h"
 #include "hardware.h"
 
-static u32 chip_revision;
-
-int imx6q_revision(void)
-{
-       return chip_revision;
-}
-
 static void __init imx6q_init_revision(void)
 {
        u32 rev = imx_anatop_get_digprog();
+       u32 chip_revision;
 
        switch (rev & 0xff) {
        case 0:
@@ -64,6 +58,7 @@ static void __init imx6q_init_revision(void)
        }
 
        mxc_set_cpu_type(rev >> 16 & 0xff);
+       imx_set_soc_revision(chip_revision);
 }
 
 static void imx6q_restart(enum reboot_mode mode, const char *cmd)
@@ -191,7 +186,7 @@ static void __init imx6q_1588_init(void)
 static void __init imx6q_init_machine(void)
 {
        imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
-                             imx6q_revision());
+                             imx_get_soc_revision());
 
        imx6q_enet_phy_init();
 
@@ -270,7 +265,7 @@ static void __init imx6q_init_late(void)
         * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
         * to run cpuidle on them.
         */
-       if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
+       if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
                imx6q_cpuidle_init();
 
        if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {