unsigned int int_crt_support:1;
        unsigned int lvds_use_ssc:1;
        unsigned int display_clock_mode:1;
+       unsigned int fdi_rx_polarity_inverted:1;
        int lvds_ssc_freq;
        unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
        struct {
 
 #define _TRANSB_CHICKEN2        0xf1064
 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
 #define  TRANS_CHICKEN2_TIMING_OVERRIDE                (1<<31)
-
+#define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED  (1<<29)
 
 #define SOUTH_CHICKEN1         0xc2000
 #define  FDIA_PHASE_SYNC_SHIFT_OVR     19
 
                dev_priv->lvds_ssc_freq =
                        intel_bios_ssc_frequency(dev, general->ssc_freq);
                dev_priv->display_clock_mode = general->display_clock_mode;
-               DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d\n",
+               dev_priv->fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
+               DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
                              dev_priv->int_tv_support,
                              dev_priv->int_crt_support,
                              dev_priv->lvds_use_ssc,
                              dev_priv->lvds_ssc_freq,
-                             dev_priv->display_clock_mode);
+                             dev_priv->display_clock_mode,
+                             dev_priv->fdi_rx_polarity_inverted);
        }
 }
 
 
         /* bits 3 */
        u8 disable_smooth_vision:1;
        u8 single_dvi:1;
-       u8 rsvd9:6; /* finish byte */
+       u8 rsvd9:1;
+       u8 fdi_rx_polarity_inverted:1;
+       u8 rsvd10:4; /* finish byte */
 
         /* bits 4 */
        u8 legacy_monitor_detect;
 
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        int pipe;
+       uint32_t val;
 
        /*
         * On Ibex Peak and Cougar Point, we need to disable clock
        /* The below fixes the weird display corruption, a few pixels shifted
         * downward, on (only) LVDS of some HP laptops with IVY.
         */
-       for_each_pipe(pipe)
-               I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
+       for_each_pipe(pipe) {
+               val = TRANS_CHICKEN2_TIMING_OVERRIDE;
+               if (dev_priv->fdi_rx_polarity_inverted)
+                       val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
+               I915_WRITE(TRANS_CHICKEN2(pipe), val);
+       }
        /* WADP0ClockGatingDisable */
        for_each_pipe(pipe) {
                I915_WRITE(TRANS_CHICKEN1(pipe),