return 0;
 }
 
+static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host,
+                                  unsigned char width)
+{
+       switch (width) {
+       case MMC_BUS_WIDTH_1:
+               mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
+               break;
+       case MMC_BUS_WIDTH_4:
+               mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
+               break;
+       case MMC_BUS_WIDTH_8:
+               mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
+               break;
+       }
+}
+
 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
        struct sunxi_mmc_host *host = mmc_priv(mmc);
                break;
        }
 
-       /* set bus width */
-       switch (ios->bus_width) {
-       case MMC_BUS_WIDTH_1:
-               mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
-               break;
-       case MMC_BUS_WIDTH_4:
-               mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
-               break;
-       case MMC_BUS_WIDTH_8:
-               mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
-               break;
-       }
+       sunxi_mmc_set_bus_width(host, ios->bus_width);
 
        /* set ddr mode */
        rval = mmc_readl(host, REG_GCTRL);