drm/i915: pass dev_priv explicitly to DSPPOS

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPPOS register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/fbe6b94f03926175611b51c5054466dd27656d2a.1716469091.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 34760ecd5d3493d4ce73d8cf6bcd5faad571da04..b23135ed1a388691c6010e7219567cdc7a893cf2 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -437,7 +437,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
                 * generator but let's assume we still need to
                 * program whatever is there.
                 */
-               intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
+               intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane),
                                  DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x));
                intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
                                  DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1));

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 049114620d931cefff2c0b9fcaf51db2af1a99ea..13a49550c456b4bb71abae5436ec9faa4c3311b5 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -53,7 +53,7 @@
 #define DSPSTRIDE(dev_priv, plane)             _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
 
 #define _DSPAPOS                               0x7018C /* pre-g4x */
-#define DSPPOS(plane)                          _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
+#define DSPPOS(dev_priv, plane)                        _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
 #define   DISP_POS_Y_MASK              REG_GENMASK(31, 16)
 #define   DISP_POS_Y(y)                        REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
 #define   DISP_POS_X_MASK              REG_GENMASK(15, 0)

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 02c5dafc0c93e388315db725bf5064c3980e3cc4..00dd2b647c8307f992d0134208fd0f43286fca67 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -168,7 +168,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(DSPCNTR(dev_priv, PIPE_A));
        MMIO_D(DSPADDR(dev_priv, PIPE_A));
        MMIO_D(DSPSTRIDE(dev_priv, PIPE_A));
-       MMIO_D(DSPPOS(PIPE_A));
+       MMIO_D(DSPPOS(dev_priv, PIPE_A));
        MMIO_D(DSPSIZE(PIPE_A));
        MMIO_D(DSPSURF(PIPE_A));
        MMIO_D(DSPOFFSET(PIPE_A));
@@ -177,7 +177,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(DSPCNTR(dev_priv, PIPE_B));
        MMIO_D(DSPADDR(dev_priv, PIPE_B));
        MMIO_D(DSPSTRIDE(dev_priv, PIPE_B));
-       MMIO_D(DSPPOS(PIPE_B));
+       MMIO_D(DSPPOS(dev_priv, PIPE_B));
        MMIO_D(DSPSIZE(PIPE_B));
        MMIO_D(DSPSURF(PIPE_B));
        MMIO_D(DSPOFFSET(PIPE_B));
@@ -186,7 +186,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(DSPCNTR(dev_priv, PIPE_C));
        MMIO_D(DSPADDR(dev_priv, PIPE_C));
        MMIO_D(DSPSTRIDE(dev_priv, PIPE_C));
-       MMIO_D(DSPPOS(PIPE_C));
+       MMIO_D(DSPPOS(dev_priv, PIPE_C));
        MMIO_D(DSPSIZE(PIPE_C));
        MMIO_D(DSPSURF(PIPE_C));
        MMIO_D(DSPOFFSET(PIPE_C));