drm/msm/dpu: enable merge_3d support on sm8150/sm8250

Handle new merge_3d block setup in dpu encoder code. Pass correct mode
and id. Note, that merge_3d blocks are not handled via usual RM
reservation mechanism, as each merge_3d block is tied to two PPs, so by
reserving PP you get merge_3d automatically.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index a0d8aeec3e7594740358c5d25de7c91b5d91d06e..9a69fad832cdeae72535c0084a83250cf1974e5a 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -5,6 +5,7 @@
 #define pr_fmt(fmt)    "[drm:%s:%d] " fmt, __func__, __LINE__
 #include "dpu_encoder_phys.h"
 #include "dpu_hw_interrupts.h"
+#include "dpu_hw_merge3d.h"
 #include "dpu_core_irq.h"
 #include "dpu_formats.h"
 #include "dpu_trace.h"
@@ -282,6 +283,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
        intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
        intf_cfg.stream_sel = 0; /* Don't care value for video mode */
        intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+       if (phys_enc->hw_pp->merge_3d)
+               intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id;
 
        spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
        phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
@@ -295,6 +298,12 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
                                true,
                                phys_enc->hw_pp->idx);
 
+       if (phys_enc->hw_pp->merge_3d) {
+               struct dpu_hw_merge_3d *merge_3d = to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d);
+
+               merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d);
+       }
+
        spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 
        programmable_fetch_config(phys_enc, &timing_params);
@@ -451,6 +460,8 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
                goto skip_flush;
 
        ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
+       if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d)
+               ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->id);
 
 skip_flush:
        DPU_DEBUG_VIDENC(phys_enc,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
index 065996b3ece90adeb24c26c8b5a1d6b0c56fd669..6902b9b95c8e046dc83dc70bb29fc9d342b9b36b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
@@ -119,6 +119,7 @@ struct dpu_hw_pingpong {
        /* pingpong */
        enum dpu_pingpong idx;
        const struct dpu_pingpong_cfg *caps;
+       struct dpu_hw_blk *merge_3d;
 
        /* ops */
        struct dpu_hw_pingpong_ops ops;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 7ddc26f51d8e978b9492ed4adc4532c5454fcc69..0ae8a36ffcff38b656a571c7347384a398014c74 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -161,6 +161,8 @@ int dpu_rm_init(struct dpu_rm *rm,
                                rc);
                        goto fail;
                }
+               if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX)
+                       hw->merge_3d = rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0];
                rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base;
        }