* "last user address" is set even if bootp is used without parameters
(and it uses default address).
+======================================================================
+Modifications since 0.7.1:
+======================================================================
+
+* Fix in cpu/mpc8xx/fec.c (by Dave Ellis): The PHY discovery code
+ must be called after the FEC is enabled, since it uses the FEC to
+ talk to the PHY.
+
+* EEPROM Speedup; allow other addresses (by Dave Ellis)
+
+* Added SXNI855T configuration (by Dave Ellis)
+
======================================================================
Modifications for 0.7.1:
======================================================================
* There is a new environment variable "autoload"; if set to a string
beginning with 'n' ("no autoload") the "bootp" command will issue a
- BOOTP request to detremine the system configuration parameters from
+ BOOTP request to determine the system configuration parameters from
the BOOTP server, but it will not automatically start TFTP to
download the boot file
E: ddickey@charter.net
D: FADS Support
+N: Dave Ellis
+E: DGE@sixnetio.com
+D: EEPROM Speedup, SXNI855T port
+
N: Marius Groeger
E: mgroeger@sysgo.de
D: MBX Support, board specific function interface
CPCI405 ADCIOP \
cogent_mpc8xx \
GENIETV \
+ SXNI855T \
cogent_mpc8260 hymod \
Sandpoint8240 \
hermes IP860 \
echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+SXNI855T_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = sixnet" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
FADS823_config \
FADS850SAR_config \
FADS860T_config: unconfig
- board/cpci405 Files specific to CPCI405 boards
- board/etx094 Files specific to ETX_094 boards
- board/fads Files specific to FADS boards
+- board/sixnet Files specific to SIXNET boards
- board/genietv Files specific to GENIETV boards
- board/hermes Files specific to HERMES boards
- board/hymod Files specific to HYMOD boards
CONFIG_ADCIOP, CONFIG_COGENT, CONFIG_CPCI405, CONFIG_ETX094,
CONFIG_FADS, CONFIG_FPS850L, CONFIG_HERMES, CONFIG_IP860,
CONFIG_IVMS8, CONFIG_MBX, CONFIG_SM850, CONFIG_SPD823TS,
- CONFIG_TQM823L, CONFIG_TQM850L, CONFIG_TQM855L, CONFIG_TQM860L
+ CONFIG_TQM823L, CONFIG_TQM850L, CONFIG_TQM855L, CONFIG_TQM860L,
+ CONFIG_SXNI855T
--- FIXME --- not tested yet:
CONFIG_TQM860, CONFIG_ADS,
CONFIG_RPXLITE, CONFIG_RPXCLASSIC, CONFIG_BSEIP,
- CFG_ENV_SIZE:
These two #defines specify the offset and size of the
- environment area withon the ttal memory of your EEPROM.
+ environment area within the total memory of your EEPROM.
Please note that the environment is read-only as long as the monitor
make NAME_config
where "NAME_config" is the name of one of the existing
-configurations; the following names are suported:
+configurations; the following names are supported:
TQM823L_config
TQM850L_config
SPD823TS_config
cogent_mpc8xx_config
MBX_config
+ SXNI855T_config
If the system board that you have is not listed, then you will need
#define PB_SCL 0x00000020 /* PB 26 */
#define PB_SDA 0x00000010 /* PB 27 */
+#define I2C_ACK 0 /* PB_SDA level to ack a byte */
+#define I2C_NOACK 1 /* PB_SDA level to noack a byte */
#define SET_PB_BIT(bit) do { \
immr->im_cpm.cp_pbdir |= bit; /* output */ \
#define RESET_PB_BIT(bit) do { \
immr->im_cpm.cp_pbdir |= bit; /* output */ \
- immr->im_cpm.cp_pbdat &= ~bit; /* set 8 */ \
+ immr->im_cpm.cp_pbdat &= ~bit; /* set 0 */ \
udelay (5); \
} while (0)
+#define RESET_PB_BIT1(bit) do { \
+ immr->im_cpm.cp_pbdir |= bit; /* output */ \
+ immr->im_cpm.cp_pbdat &= ~bit; /* set 0 */ \
+ udelay (1); \
+ } while (0)
+
/*-----------------------------------------------------------------------
* Functions
*/
static void send_start (void);
static void send_stop (void);
-#if 0
-static void send_ack (void);
-#endif
-static void send_ack1 (void);
+static void send_ack (int);
static void rcv_ack (void);
static void send_data_1 (void);
static void send_data_0 (void);
static void read_addr (uchar addr);
static void write_addr (uchar addr);
static int read_bit (void);
-static uchar read_byte (void);
+static uchar read_byte (int);
static void write_byte (uchar byte);
/*-----------------------------------------------------------------------
}
/*-----------------------------------------------------------------------
+ * ack should be I2C_ACK or I2C_NOACK
*/
-#if 0
-static void send_ack (void)
+static void send_ack (int ack)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
RESET_PB_BIT (PB_SCL);
- RESET_PB_BIT (PB_SDA);
- SET_PB_BIT (PB_SCL);
- udelay (5);
-}
-#endif
-
-/*-----------------------------------------------------------------------
- */
-static void send_ack1 (void)
-{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
-
- RESET_PB_BIT (PB_SCL);
- SET_PB_BIT (PB_SDA);
+ if (ack == I2C_ACK)
+ RESET_PB_BIT (PB_SDA);
+ else
+ SET_PB_BIT (PB_SDA);
SET_PB_BIT (PB_SCL);
udelay (5);
RESET_PB_BIT (PB_SCL);
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
- RESET_PB_BIT (PB_SCL);
+ RESET_PB_BIT1(PB_SCL);
SET_PB_BIT (PB_SDA);
SET_PB_BIT (PB_SCL);
- udelay (5);
}
/*-----------------------------------------------------------------------
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
- RESET_PB_BIT (PB_SCL);
+ RESET_PB_BIT1(PB_SCL);
RESET_PB_BIT (PB_SDA);
SET_PB_BIT (PB_SCL);
- udelay (5);
}
/*-----------------------------------------------------------------------
* addr & 0xF0 -> 0xA0 = Device Type Identifier
- * addr & 0x0E -> bank_num << 1
+ * addr & 0x0E -> bank_num or device address << 1
* addr & 0x01 -> 1 = read, 0 = write
*/
static void write_addr (uchar addr)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
int bit;
- immr->im_cpm.cp_pbdir &= ~PB_SDA; /* input */
- udelay (5);
RESET_PB_BIT (PB_SCL);
- udelay (5);
SET_PB_BIT (PB_SCL);
bit = (immr->im_cpm.cp_pbdat & PB_SDA) ? 1 : 0;
- udelay (5);
return (bit);
}
/*-----------------------------------------------------------------------
+ * if last == 0, ACK the byte so can continue reading
+ * else NO ACK to end the read
*/
-static uchar read_byte (void)
+static uchar read_byte (int last)
{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
uchar byte = 0;
int i;
+ immr->im_cpm.cp_pbdir &= ~PB_SDA; /* input */
+ udelay (5);
+
for (i=0; i<8; ++i) {
byte = (byte << 1) | read_bit();
}
- send_ack1 ();
+ if (!last)
+ send_ack (I2C_ACK);
+ else
+ send_ack (I2C_NOACK);
return byte;
}
}
/*-----------------------------------------------------------------------
+ *
+ * for CONFIG_I2C_X defined (16-bit EEPROM address) offset is
+ * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
+ *
+ * for CONFIG_I2C_X not defined (8-bit EEPROM page address) offset is
+ * 0x00000nxx for EEPROM address selectors and page number at n.
*/
void eeprom_read (unsigned offset, uchar *buffer, unsigned cnt)
{
unsigned i, blk_off, blk_num;
+ int last;
- for (i=0; i<cnt; ++i) {
+ i = 0;
+ while (i<cnt) {
+#ifndef CONFIG_I2C_X
blk_num = (offset + i) >> 8;
blk_off = (offset + i) & 0xFF;
-
-#ifndef CONFIG_I2C_X
write_addr (blk_num);
write_byte (blk_off);
- send_start ();
- read_addr (blk_num);
#else
- write_addr (0); /* assume addr selectors hardwired to 0 */
- write_byte (blk_num); /* upper address octet */
- write_byte (blk_off); /* lower address octet */
- send_start ();
- read_addr (0); /* assume addr selectors hardwired to 0 */
+ blk_num = (offset + i) >> 16; /* addr selectors */
+ blk_off = (offset + i) & 0xFFFF;/* 16-bit address in EEPROM */
+
+ write_addr (blk_num);
+ write_byte (blk_off >> 8); /* upper address octet */
+ write_byte (blk_off & 0xff); /* lower address octet */
#endif /* CONFIG_I2C_X */
- *buffer++ = read_byte();
+
+ send_start ();
+ read_addr (blk_num);
+
+ /* Read data until done or would cross a page boundary.
+ * We must write the address again when changing pages
+ * because the next page may be in a different device.
+ */
+ do {
+ ++i;
+ last = (i == cnt || ((offset + i) & 0xFF) == 0);
+ *buffer++ = read_byte(last);
+ } while (!last);
send_stop ();
}
}
/*-----------------------------------------------------------------------
+ *
+ * for CONFIG_I2C_X defined (16-bit EEPROM address) offset is
+ * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
+ *
+ * for CONFIG_I2C_X not defined (8-bit EEPROM page address) offset is
+ * 0x00000nxx for EEPROM address selectors and page number at n.
*/
void eeprom_write (unsigned offset, uchar *buffer, unsigned cnt)
{
unsigned i, blk_off, blk_num;
- for (i=0; i<cnt; ++i) {
+ i = 0;
+ while (i < cnt) {
+#ifndef CONFIG_I2C_X
blk_num = (offset + i) >> 8;
blk_off = (offset + i) & 0xFF;
-#ifndef CONFIG_I2C_X
write_addr (blk_num);
write_byte (blk_off);
#else
- write_addr (0); /* assume addr selectors hardwired to 0 */
- write_byte (blk_num); /* upper address octet */
- write_byte (blk_off); /* lower address octet */
+ blk_num = (offset + i) >> 16; /* addr selectors */
+ blk_off = (offset + i) & 0xFFFF;/* 16-bit address in EEPROM */
+
+ write_addr (blk_num);
+ write_byte (blk_off >> 8); /* upper address octet */
+ write_byte (blk_off & 0xff); /* lower address octet */
#endif /* CONFIG_I2C_X */
+
+#if defined(CFG_EEPROM_PAGE_WRITE_BITS)
+#define PAGE_OFFSET(x) ((x) & ((1 << CFG_EEPROM_PAGE_WRITE_BITS) - 1))
+ /* Write data until done or would cross a write page boundary.
+ * We must write the address again when changing pages
+ * because the address counter only increments within a page.
+ */
+ do {
+ write_byte (*buffer++);
+ ++i;
+ } while (i < cnt && PAGE_OFFSET(offset + i) != 0);
+#else
write_byte (*buffer++);
+ ++i;
+#endif
send_stop ();
}
}
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o ../ip860/eeprom.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# SIXNET boards
+#
+
+TEXT_BASE = 0x02800000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+
+int flash_write (uchar *, ulong, ulong);
+flash_info_t *addr2info (ulong);
+
+static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+static int flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET 0x01
+#define FLAG_PROTECT_CLEAR 0x02
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ unsigned long size_b0, size_b1;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
+ {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN)
+ {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",size_b0, size_b0<<20);
+ }
+
+ if (FLASH_BASE1_PRELIM != 0x0) {
+ size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+ if (size_b1 > size_b0) {
+ printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",size_b1, size_b1<<20,size_b0, size_b0<<20);
+
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[0].sector_count = -1;
+ flash_info[1].sector_count = -1;
+ flash_info[0].size = 0;
+ flash_info[1].size = 0;
+ return (0);
+ }
+ } else {
+ size_b1 = 0;
+ }
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = CFG_OR0_PRELIM;
+ memctl->memc_br0 = CFG_BR0_PRELIM;
+
+ /* Re-do sizing to get full correct info */
+ size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,CFG_FLASH_BASE+CFG_MONITOR_LEN-1, &flash_info[0]);
+
+ if (size_b1)
+ {
+ memctl->memc_or1 = CFG_OR1_PRELIM;
+ memctl->memc_br1 = CFG_BR1_PRELIM;
+
+ /* Re-do sizing to get full correct info */
+ size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), &flash_info[1]);
+
+ flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE+CFG_MONITOR_LEN-1, &flash_info[1]);
+ }
+ else
+ {
+ memctl->memc_or1 = CFG_OR1_PRELIM;
+ memctl->memc_br1 = CFG_BR1_PRELIM;
+
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+
+ return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ * Check or set protection status for monitor sectors
+ *
+ * The monitor always occupies the _first_ part of the _first_ Flash bank.
+ */
+static int flash_protect (int flag, ulong from, ulong to, flash_info_t *info)
+{
+ ulong b_end = info->start[0] + info->size - 1; /* bank end address */
+ int rc = 0;
+ int first = -1;
+ int last = -1;
+ int i;
+
+ if (to < info->start[0]) {
+ return (0);
+ }
+
+ for (i=0; i<info->sector_count; ++i) {
+ ulong end; /* last address in current sect */
+ short s_end;
+
+ s_end = info->sector_count - 1;
+
+ end = (i == s_end) ? b_end : info->start[i + 1] - 1;
+
+ if (from > end) {
+ continue;
+ }
+ if (to < info->start[i]) {
+ continue;
+ }
+
+ if (from == info->start[i]) {
+ first = i;
+ if (last < 0) {
+ last = s_end;
+ }
+ }
+ if (to == end) {
+ last = i;
+ if (first < 0) {
+ first = 0;
+ }
+ }
+ }
+
+ for (i=first; i<=last; ++i) {
+ if (flag & FLAG_PROTECT_CLEAR) {
+ info->protect[i] = 0;
+ } else if (flag & FLAG_PROTECT_SET) {
+ info->protect[i] = 1;
+ }
+ if (info->protect[i]) {
+ rc = 1;
+ }
+ }
+ return (rc);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ /* set up sector start adress table */
+ if (info->flash_id & FLASH_BTYPE)
+ {
+ /* set sector offsets for bottom boot block type */
+ for (i = 0; i < info->sector_count; i++)
+ {
+ info->start[i] = base + (i * 0x00040000);
+ }
+ }
+ else
+ {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ for (; i >= 0; i--)
+ {
+ info->start[i] = base + i * 0x00040000;
+ }
+ }
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK)
+ {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK)
+ {
+ case FLASH_AM040B: printf ("AM29F040B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM040T: printf ("AM29F040T (4 Mbit, top boot sect)\n");
+ break;
+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+
+ for (i=0; i<info->sector_count; ++i)
+ {
+ if ((i % 5) == 0)
+ {
+ printf ("\n ");
+ }
+
+ printf (" %08lX%s", info->start[i],info->protect[i] ? " (RO)" : " " );
+ }
+
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+#if 0
+ ulong base = (ulong)addr;
+#endif
+ uchar value;
+
+ /* Write auto select command: read Manufacturer ID */
+#if 0
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+ addr[0x0555] = 0x00900090;
+#else
+ addr[0x0555] = 0xAAAAAAAA;
+ addr[0x02AA] = 0x55555555;
+ addr[0x0555] = 0x90909090;
+#endif
+
+ value = addr[0];
+
+ switch (value)
+ {
+ case AMD_MANUFACT:case 0x01:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+
+ case FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ break;
+ }
+
+ value = addr[1]; /* device ID */
+
+ switch (value)
+ {
+ case AMD_ID_F040B:
+ info->flash_id += FLASH_AM040B;
+ info->sector_count = 8;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+#if 0 /* enable when device IDs are available */
+ case AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 67;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+
+ case AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 67;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+#endif
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+#if 0
+ /* set up sector start adress table */
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00008000;
+ info->start[2] = base + 0x0000C000;
+ info->start[3] = base + 0x00010000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000) - 0x00060000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000C000;
+ info->start[i--] = base + info->size - 0x00010000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00020000;
+ }
+ }
+#else
+ flash_get_offsets ((ulong)addr, &flash_info[0]);
+#endif
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++)
+ {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr = (volatile unsigned long *)(info->start[i]);
+ info->protect[i] = addr[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN)
+ {
+ addr = (volatile unsigned long *)info->start[0];
+#if 0
+ *addr = 0x00F000F0; /* reset bank */
+#else
+ *addr = 0xF0F0F0F0; /* reset bank */
+#endif
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ vu_long *addr = (vu_long*)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return;
+ }
+
+ if ((info->flash_id == FLASH_UNKNOWN) ||
+ (info->flash_id > FLASH_AMD_COMP)) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+#if 0
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+ addr[0x0555] = 0x00800080;
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+#else
+ addr[0x0555] = 0xAAAAAAAA;
+ addr[0x02AA] = 0x55555555;
+ addr[0x0555] = 0x80808080;
+ addr[0x0555] = 0xAAAAAAAA;
+ addr[0x02AA] = 0x55555555;
+#endif
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (vu_long*)(info->start[sect]);
+#if 0
+ addr[0] = 0x00300030;
+#else
+ addr[0] = 0x30303030;
+#endif
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (vu_long*)(info->start[l_sect]);
+#if 0
+ while ((addr[0] & 0x00800080) != 0x00800080)
+#else
+ while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
+#endif
+ {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+ addr = (volatile unsigned long *)info->start[0];
+#if 0
+ addr[0] = 0x00F000F0; /* reset bank */
+#else
+ addr[0] = 0xF0F0F0F0; /* reset bank */
+#endif
+
+ printf (" done\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+flash_info_t *addr2info (ulong addr)
+{
+ flash_info_t *info;
+ int i;
+
+ for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+ if ((addr >= info->start[0]) &&
+ (addr < (info->start[0] + info->size)) ) {
+ return (info);
+ }
+ }
+
+ return (NULL);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Make sure all target addresses are within Flash bounds,
+ * and no protected sectors are hit.
+ * Returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - target range includes protected sectors
+ * 8 - target address not in Flash memory
+ */
+int flash_write (uchar *src, ulong addr, ulong cnt)
+{
+ int i;
+ ulong end = addr + cnt - 1;
+ flash_info_t *info_first = addr2info (addr);
+ flash_info_t *info_last = addr2info (end );
+ flash_info_t *info;
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ if (!info_first || !info_last) {
+ return (8);
+ }
+
+ for (info = info_first; info <= info_last; ++info) {
+ ulong b_end = info->start[0] + info->size; /* bank end addr */
+ short s_end = info->sector_count - 1;
+ for (i=0; i<info->sector_count; ++i) {
+ ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
+
+ if ((end >= info->start[i]) && (addr < e_addr) &&
+ (info->protect[i] != 0) ) {
+ return (4);
+ }
+ }
+ }
+
+ /* finally write data to flash */
+ for (info = info_first; info <= info_last && cnt>0; ++info) {
+ ulong len;
+
+ len = info->start[0] + info->size - addr;
+ if (len > cnt)
+ len = cnt;
+ if ((i = write_buff(info, src, addr, len)) != 0) {
+ return (i);
+ }
+ cnt -= len;
+ addr += len;
+ src += len;
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long*)(info->start[0]);
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+#if 0
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+ addr[0x0555] = 0x00A000A0;
+#else
+ addr[0x0555] = 0xAAAAAAAA;
+ addr[0x02AA] = 0x55555555;
+ addr[0x0555] = 0xA0A0A0A0;
+#endif
+
+ *((vu_long *)dest) = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+#if 0
+ while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
+#else
+ while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
+#endif
+ {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8xx/start.o (.text)
+ common/environment.o(.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <config.h>
+#include "mpc8xx.h"
+#include "sixnet.h"
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+#if defined(CONFIG_DRAM_50MHZ)
+/* 50MHz tables */
+const uint dram_60ns[] =
+{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
+ 0x00ffec00, 0x37ffec47, 0xffffffff, 0xffffffff,
+ 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
+ 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
+ 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
+ 0x3fffc847, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
+ 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+ 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
+ 0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+const uint dram_70ns[] =
+{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
+ 0x00ffcc00, 0x37ffcc47, 0xffffffff, 0xffffffff,
+ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
+ 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
+ 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
+ 0x00ffec00, 0x3fffec47, 0xffffffff, 0xffffffff,
+ 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
+ 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+ 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
+ 0x7fffcc06, 0xffffcc85, 0xffffcc05, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+const uint edo_60ns[] =
+{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
+ 0x00f3ec00, 0x37f7ec47, 0xffffffff, 0xffffffff,
+ 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
+ 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
+ 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
+ 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+ 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
+ 0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+const uint edo_70ns[] =
+{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
+ 0x00f3cc00, 0x37f7cc47, 0xffffffff, 0xffffffff,
+ 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
+ 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
+ 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
+ 0x33f7cc47, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
+ 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+ 0x0cafcc00, 0x33bfcc47, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
+ 0x7fffcc04, 0xffffcc86, 0xffffcc05, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+#elif defined(CONFIG_DRAM_25MHZ)
+
+/* 25MHz tables */
+
+const uint dram_60ns[] =
+{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
+ 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
+ 0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+ 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+ 0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+const uint dram_70ns[] =
+{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
+ 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
+ 0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+ 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+ 0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+const uint edo_60ns[] =
+{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
+ 0x08f3cc00, 0x3ff7cc47, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
+ 0x08afcc48, 0x39bfcc47, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+const uint edo_70ns[] =
+{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
+ 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
+ 0x3ff7cc47, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
+ 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
+ 0x37bfcc47, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
+
+
+#else
+#error dram not correct defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ * returns 0 if recognized, -1 if unknown
+ */
+
+int checkboard (void)
+{
+ uint k;
+
+ k = (*((uint *)BCSR3) >> 24) & 0x3f;
+
+ switch(k)
+ {
+ case 0x22 :
+ printf("FADS simulating SIXNET SXNI855T\n");
+ break;
+
+ case 0xff :
+ printf("SIXNET SXNI855T");
+ break;
+
+ default :
+ printf("unknown board (0x%02x)\n", k);
+ return -1;
+ }
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+int _draminit(uint base, uint noMbytes, uint edo, uint delay)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ /* init upm */
+
+ switch(delay)
+ {
+ case 70:
+ {
+ if(edo)
+ {
+ upmconfig(UPMA, (uint *) edo_70ns, sizeof(edo_70ns)/sizeof(uint));
+ }
+ else
+ {
+ upmconfig(UPMA, (uint *) dram_70ns, sizeof(dram_70ns)/sizeof(uint));
+ }
+
+ break;
+ }
+
+ case 60:
+ {
+ if(edo)
+ {
+ upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));
+ }
+ else
+ {
+ upmconfig(UPMA, (uint *) dram_60ns, sizeof(dram_60ns)/sizeof(uint));
+ }
+
+ break;
+ }
+
+ default :
+ return -1;
+ }
+
+ memctl->memc_mptpr = 0x0400; /* divide by 16 */
+
+ switch(noMbytes)
+ {
+
+ case 8: /* 8 Mbyte uses both CS3 and CS2 */
+ {
+ memctl->memc_mamr = 0x13a01114;
+ memctl->memc_or3 = 0xffc00800;
+ memctl->memc_br3 = 0x00400081 + base;
+ memctl->memc_or2 = 0xffc00800;
+ break;
+ }
+
+ case 4: /* 4 Mbyte uses only CS2 */
+ {
+ memctl->memc_mamr = 0x13a01114;
+ memctl->memc_or2 = 0xffc00800;
+ break;
+ }
+
+ case 32: /* 32 Mbyte uses both CS3 and CS2 */
+ {
+ memctl->memc_mamr = 0x13b01114;
+ memctl->memc_or3 = 0xff000800;
+ memctl->memc_br3 = 0x01000081 + base;
+ memctl->memc_or2 = 0xff000800;
+ break;
+ }
+
+ case 16: /* 16 Mbyte uses only CS2 */
+ {
+#ifdef CONFIG_ADS
+ memctl->memc_mamr = 0x60b21114;
+#else
+ memctl->memc_mamr = 0x13b01114;
+#endif
+ memctl->memc_or2 = 0xff000800;
+ break;
+ }
+
+ default:
+ return -1;
+ }
+
+ memctl->memc_br2 = 0x81 + base; /* use upma */
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void _dramdisable(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ memctl->memc_br2 = 0x00000000;
+ memctl->memc_br3 = 0x00000000;
+
+ /* maybe we should turn off upma here or something */
+}
+
+#if defined(CONFIG_SDRAM_100MHZ)
+
+/* ------------------------------------------------------------------------- */
+/* sdram table by Dan Malek */
+
+/* This has the stretched early timing so the 50 MHz
+ * processor can make the 100 MHz timing. This will
+ * work at all processor speeds.
+ */
+
+#define SDRAM_MPTPRVALUE 0x0400
+
+#define SDRAM_MBMRVALUE0 0xc3802114 /* (16-14) 50 MHz */
+#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0
+
+#define SDRAM_OR4VALUE 0xffc00a00
+#define SDRAM_BR4VALUE 0x000000c1 /* base address will be or:ed on */
+
+#define SDRAM_MARVALUE 0x88
+
+#define SDRAM_MCRVALUE0 0x80808111 /* run pattern 0x11 */
+#define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0
+
+
+const uint sdram_table[] =
+{
+ /* single read. (offset 0 in upm RAM) */
+ 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
+ 0xefbbbc00, 0x1ff77c45, 0xffffffff, 0xffffffff,
+
+ /* burst read. (offset 8 in upm RAM) */
+ 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
+ 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
+ 0x1ff77c45, 0xeffbbc04, 0x1ff77c34, 0xefeabc34,
+ 0x1fb57c35, 0xffffffff, 0xffffffff, 0xffffffff,
+
+ /* single write. (offset 18 in upm RAM) */
+ 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
+ 0x1ff77c45, 0xffffffff, 0xffffffff, 0xffffffff,
+
+ /* burst write. (offset 20 in upm RAM) */
+ 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,
+ 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+
+ /* refresh. (offset 30 in upm RAM) */
+ 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
+ 0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+
+ /* exception. (offset 3c in upm RAM) */
+ 0xeffffc06, 0x1ffffc07, 0xffffffff, 0xffffffff };
+
+#elif defined(CONFIG_SDRAM_50MHZ)
+
+/* ------------------------------------------------------------------------- */
+/* sdram table stolen from the fads manual */
+/* for chip MB811171622A-100 */
+
+/* this table is for 32-50MHz operation */
+
+#define _not_used_ 0xffffffff
+
+#define SDRAM_MPTPRVALUE 0x0400
+
+#define SDRAM_MBMRVALUE0 0x80802114 /* refresh at 32MHz */
+#define SDRAM_MBMRVALUE1 0x80802118
+
+#define SDRAM_OR4VALUE 0xffc00a00
+#define SDRAM_BR4VALUE 0x000000c1 /* base address will be or:ed on */
+
+#define SDRAM_MARVALUE 0x88
+
+#define SDRAM_MCRVALUE0 0x80808105
+#define SDRAM_MCRVALUE1 0x80808130
+
+const uint sdram_table[] =
+{
+ /* single read. (offset 0 in upm RAM) */
+ 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+ 0x1ff77c47,
+
+ /* MRS initialization (offset 5) */
+
+ 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+ /* burst read. (offset 8 in upm RAM) */
+ 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+ 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+ _not_used_, _not_used_, _not_used_, _not_used_,
+ _not_used_, _not_used_, _not_used_, _not_used_,
+
+ /* single write. (offset 18 in upm RAM) */
+ 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+ _not_used_, _not_used_, _not_used_, _not_used_,
+
+ /* burst write. (offset 20 in upm RAM) */
+ 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+ 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
+ _not_used_, _not_used_, _not_used_, _not_used_,
+ _not_used_, _not_used_, _not_used_, _not_used_,
+
+ /* refresh. (offset 30 in upm RAM) */
+ 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ 0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+ _not_used_, _not_used_, _not_used_, _not_used_,
+
+ /* exception. (offset 3c in upm RAM) */
+ 0x7ffffc07, _not_used_, _not_used_, _not_used_ };
+
+/* ------------------------------------------------------------------------- */
+#else
+#error SDRAM not correctly configured
+#endif
+
+int _initsdram(uint base, uint noMbytes)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ if(noMbytes != 4)
+ {
+ return -1;
+ }
+
+ upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
+
+ memctl->memc_mptpr = SDRAM_MPTPRVALUE;
+
+ /* Configure the refresh (mostly). This needs to be
+ * based upon processor clock speed and optimized to provide
+ * the highest level of performance. For multiple banks,
+ * this time has to be divided by the number of banks.
+ * Although it is not clear anywhere, it appears the
+ * refresh steps through the chip selects for this UPM
+ * on each refresh cycle.
+ * We have to be careful changing
+ * UPM registers after we ask it to run these commands.
+ */
+
+ memctl->memc_mbmr = SDRAM_MBMRVALUE0;
+ memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */
+
+ udelay(200);
+
+ /* Now run the precharge/nop/mrs commands.
+ */
+
+ memctl->memc_mcr = 0x80808111; /* run pattern 0x11 */
+
+ udelay(200);
+
+ /* Run 8 refresh cycles */
+
+ memctl->memc_mcr = SDRAM_MCRVALUE0;
+
+ udelay(200);
+
+ memctl->memc_mbmr = SDRAM_MBMRVALUE1;
+ memctl->memc_mcr = SDRAM_MCRVALUE1;
+
+ udelay(200);
+
+ memctl->memc_mbmr = SDRAM_MBMRVALUE0;
+
+ memctl->memc_or4 = SDRAM_OR4VALUE;
+ memctl->memc_br4 = SDRAM_BR4VALUE | base;
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void _sdramdisable(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ memctl->memc_br4 = 0x00000000;
+
+ /* maybe we should turn off upmb here or something */
+}
+
+/* ------------------------------------------------------------------------- */
+
+int initsdram(uint base, uint *noMbytes)
+{
+ uint m = 4;
+
+ /* This is needed only for the FADS board emulating the SIXNET board.
+ * The SXNI855T has no BCSRs.
+ */
+ /* enable sdram, _fads_sdraminit needs access to sdram */
+ *((uint *)BCSR1) |= BCSR1_SDRAM_EN;
+ *noMbytes = m;
+
+ if (!_initsdram(base, m)) {
+ return 0;
+ }
+ else {
+ *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */
+
+ _sdramdisable();
+
+ return -1;
+ }
+}
+
+long int initdram (int board_type)
+{
+ /* FADS: has 4MB SDRAM, put DRAM above it */
+ uint base = (unsigned long)0x00400000;
+ uint k, m, s;
+
+ k = (*((uint *)BCSR2) >> 23) & 0x0f;
+
+ m = 0;
+
+ switch(k & 0x3) {
+ /* "MCM36100 / MT8D132X" */
+ case 0x00 :
+ m = 4;
+ break;
+
+ /* "MCM36800 / MT16D832X" */
+ case 0x01 :
+ m = 32;
+ break;
+ /* "MCM36400 / MT8D432X" */
+ case 0x02 :
+ m = 16;
+ break;
+ /* "MCM36200 / MT16D832X ?" */
+ case 0x03 :
+ m = 8;
+ break;
+
+ }
+
+ switch(k >> 2) {
+ case 0x02 :
+ k = 70;
+ break;
+
+ case 0x03 :
+ k = 60;
+ break;
+
+ default :
+ printf("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
+ k = 70;
+ }
+
+ /* the FADS is missing this bit, all rams treated as non-edo */
+ s = 0;
+
+ if(!_draminit(base, m, s, k)) {
+ uint sdramsz;
+ *((uint *)BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */
+
+ if (!initsdram(0x00000000, &sdramsz)) {
+ m += sdramsz;
+ printf("(%u MB SDRAM) ", sdramsz);
+ } else {
+ _dramdisable();
+
+ /********************************
+ *DRAM ERROR, HALT PROCESSOR
+ *********************************/
+ while(1);
+
+ return -1;
+ }
+
+ return (m << 20);
+ }
+ else {
+ _dramdisable();
+
+ /********************************
+ *DRAM ERROR, HALT PROCESSOR
+ *********************************/
+ while(1);
+
+ return -1;
+ }
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_PCMCIA
+
+#ifdef CFG_PCMCIA_MEM_ADDR
+volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
+#endif
+
+int pcmcia_init(void)
+{
+ volatile pcmconf8xx_t *pcmp;
+ uint v, slota, slotb;
+
+ /*
+ ** Enable the PCMCIA for a Flash card.
+ */
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+
+ /* Set all slots to zero by default. */
+ pcmp->pcmc_pgcra = 0;
+ pcmp->pcmc_pgcrb = 0;
+#ifdef PCMCIA_SLOT_A
+ pcmp->pcmc_pgcra = 0x40;
+#endif
+#ifdef PCMCIA_SLOT_B
+ pcmp->pcmc_pgcrb = 0x40;
+#endif
+
+ /* enable PCMCIA buffers */
+ *((uint *)BCSR1) &= ~BCSR1_PCCEN;
+
+ /* Check if any PCMCIA card is plugged in. */
+
+ slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
+ slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
+
+ if (!(slota || slotb))
+ {
+ printf("No card present\n");
+#ifdef PCMCIA_SLOT_A
+ pcmp->pcmc_pgcra = 0;
+#endif
+#ifdef PCMCIA_SLOT_B
+ pcmp->pcmc_pgcrb = 0;
+#endif
+ return -1;
+ }
+ else
+ printf("Card present (");
+
+ v = 0;
+
+ /* both the ADS and the FADS have a 5V keyed pcmcia connector (?)
+ **
+ ** Paolo - Yes, but i have to insert some 3.3V card in that slot on
+ ** my FADS... :-)
+ */
+
+#if defined(CONFIG_MPC860) || defined(CONFIG_MPC855)
+ switch( (pcmp->pcmc_pipr >> 30) & 3 )
+#else
+#error unknown processor type
+#endif
+ {
+ case 0x00 :
+ printf("5V");
+ v = 5;
+ break;
+ case 0x01 :
+ printf("5V and 3V");
+ v = 3; // User lower voltage if supported!
+ break;
+ case 0x03 :
+ printf("5V, 3V and x.xV");
+ v = 3; // User lower voltage if supported!
+ break;
+ }
+
+ switch(v){
+ case 3:
+ printf("; using 3V");
+ /*
+ ** Enable 3 volt Vcc.
+ */
+ *((uint *)BCSR1) &= ~BCSR1_PCCVCC1;
+ *((uint *)BCSR1) |= BCSR1_PCCVCC0;
+ break;
+ case 5:
+ printf("; using 5V");
+ /*
+ ** Enable 5 volt Vcc.
+ */
+ *((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
+ *((uint *)BCSR1) |= BCSR1_PCCVCC1;
+ break;
+
+ default:
+ *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */
+
+ printf("; unknown voltage");
+ return -1;
+ }
+ printf(")\n");
+ /* disable pcmcia reset after a while */
+
+ udelay(20);
+
+#if defined(CONFIG_MPC860) || defined(CONFIG_MPC855)
+ pcmp->pcmc_pgcra = 0;
+#else
+#error unknown processor type
+#endif
+
+ /* If you using a real hd you should give a short
+ * spin-up time. */
+#ifdef CONFIG_DISK_SPINUP_TIME
+ udelay(CONFIG_DISK_SPINUP_TIME);
+#endif
+
+ return 0;
+}
+
+#endif /* CONFIG_PCMCIA */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscellaneous platform dependent initializations while still
+ * running in flash
+ */
+
+int
+misc_init_f(void)
+{
+ /* configure the board features, such rs232 and ethernet */
+ /* These are needed only for the FADS board emulating the SIXNET board.
+ * The SXNI855T has no BCSRs.
+ */
+ *((uint *) BCSR1) &= ~CFG_BCSR1_CLEAR;
+ *((uint *) BCSR1) |= CFG_BCSR1_SET;
+ *((uint *) BCSR4) &= ~CFG_BCSR4_CLEAR;
+ *((uint *) BCSR4) |= CFG_BCSR4_SET;
+
+#if defined(FEC_ENET)
+ /* configure FADS for fast (FEC) ethernet, half-duplex */
+ /* The LXT970 needs about 50ms to recover from reset, so
+ * wait for it by discovering the PHY before leaving eth_init().
+ */
+ {
+ volatile uint *bcsr4 = (volatile uint *) BCSR4;
+ *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
+ | (BCSR4_FETHCFG0 | BCSR4_FETHFDE | BCSR4_FETHRST);
+
+ /* reset the LXT970 PHY */
+ *bcsr4 &= ~BCSR4_FETHRST;
+ udelay (10);
+ *bcsr4 |= BCSR4_FETHRST;
+ udelay (10);
+ }
+#endif
+
+ return 0; /* success */
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by FADS Monitor:
+ *
+ * Start Address Length
+ * +-----------------------+ 0xFE00_0000 Start of Flash -----------------
+ * | MON8xx code | 0xFE00_0100 Reset Vector
+ * +-----------------------+ 0xFE0?_????
+ * | (unused) |
+ * +-----------------------+ 0xFE01_FF00
+ * | Ethernet Addresses | 0x78
+ * +-----------------------+ 0xFE01_FF78
+ * | (Reserved for MON8xx) | 0x44
+ * +-----------------------+ 0xFE01_FFBC
+ * | Lock Address | 0x04
+ * +-----------------------+ 0xFE01_FFC0 ^
+ * | Hardware Information | 0x40 | MON8xx
+ * +=======================+ 0xFE02_0000 (sector border) -----------------
+ * | Autostart Header | | Applications
+ * | ... | v
+ *
+ *****************************************************************************/
hang();
}
-#ifdef CONFIG_COGENT
+#if defined(CONFIG_COGENT) || defined(CONFIG_SXNI855T)
/* miscellaneous platform dependent initialisations */
if (misc_init_f() < 0) {
printf (failed);
static uchar get_env_char_eeprom (int index)
{
uchar c;
- eeprom_read (index, &c, 1);
+ init_data_t *idata = (init_data_t*)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
+
+ /* if the EEPROM crc was bad, use the default environment */
+ if (idata->env_valid)
+ eeprom_read (index+offsetof(env_t,data), &c, 1);
+ else
+ c = default_environment[index];
+
return (c);
}
#endif /* CFG_ENV_IS_IN_EEPROM */
int getenv_r (uchar *name, uchar *buf, unsigned len)
{
int i, nxt;
- init_data_t *idata = (init_data_t*)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
- uchar (*my_get_env_char)(int);
- /* Use default environment and memory routine in case of bad CRC */
- if (idata->env_valid) {
- my_get_env_char = get_env_char;
- } else {
- my_get_env_char = get_env_char_memory;
- }
-
- for (i=0; my_get_env_char(i) != '\0'; i=nxt+1) {
+ for (i=0; get_env_char(i) != '\0'; i=nxt+1) {
int val, n;
- for (nxt=i; my_get_env_char(nxt) != '\0'; ++nxt) {
+ for (nxt=i; get_env_char(nxt) != '\0'; ++nxt) {
if (nxt >= CFG_ENV_SIZE) {
return (-1);
}
continue;
/* found; copy out */
n = 0;
- while ((len > n++) && (*buf++ = my_get_env_char(val++)) != '\0')
+ while ((len > n++) && (*buf++ = get_env_char(val++)) != '\0')
;
if (len == n)
*buf = '\0';
unsigned off;
uchar buf[64];
+ eeprom_init (); /* prepare for EEPROM read/write */
+
/* read old CRC */
eeprom_read (offsetof(env_t,crc), (uchar *)&crc, sizeof(ulong));
defined(CONFIG_IVMS8) || \
defined(CONFIG_HERMES) || \
defined(CONFIG_IP860) || \
+ defined(CONFIG_SXNI855T) || \
(defined(CONFIG_MPC860T) && defined(CONFIG_FADS))
/* XXX - FIXME - XXX
* I still don't understand why some systems work only with this
rxIdx = 0;
txIdx = 0;
+ /* Now enable the transmit and receive processing
+ */
+ fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
+
#ifdef CFG_DISCOVER_PHY
/* wait for the PHY to wake up after reset
*/
mii_discover_phy();
#endif
- /* And last, enable the transmit and receive processing
- */
- fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
-
- /* Try to fill Rx Buffer Descriptors */
+ /* And last, try to fill Rx Buffer Descriptors */
fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
return 1;
#define SICR_ENET_CLKRT ((uint)0x0000002C)
#endif /* CONFIG_IP860 */
+/*** SXNI855T ******************************************************/
+
+#if defined(CONFIG_SXNI855T)
+
+#ifdef CONFIG_FEC_ENET
+#define FEC_ENET /* use FEC for Ethernet */
+#endif /* CONFIG_FEC_ETHERNET */
+
+#endif /* CONFIG_SXNI855T */
+
/*********************************************************************/
/* SCC Event register as used by Ethernet.
#ifdef DEBUG
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
#endif
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
--- /dev/null
+/*
+ * PPCBoot configuration for SIXNET SXNI855T CPU board.
+ * This board is based on the Motorola FADS board, so this
+ * file is based on config_FADS860T.h, see it for additional
+ * credits.
+ *
+ * (C) Copyright 2000
+ * Dave Ellis, SIXNET, dge@sixnetio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This configuration is still in preliminary design, so far it
+ * works only with a FADS 860T emulating the final design.
+ */
+
+/*
+ * ### FIXME - these are still from config_FADS860T.h
+ * ff020000 -> ff02ffff : pcmcia
+ * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom
+ * ff000000 -> ff00ffff : IMAP internal in the cpu
+ * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom
+ * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#include <mpc8xx_irq.h>
+
+/* The 855T is just a stripped 860T and needs code for 860, so for now
+ * at least define 860, 860T and 855T
+ */
+#define CONFIG_MPC860 1
+#define CONFIG_MPC860T 1
+#define CONFIG_MPC855T 1
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+
+#define MPC8XX_FACT 12 /* Multiply by 12 */
+#define MPC8XX_XIN 4000000 /* 4 MHz in */
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+
+#if 1
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_BOOTCOMMAND "bootm 2800100" /* autoboot command */
+#define CONFIG_BOOTARGS ""
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/* choose SCC1 ethernet (10BASET on motherboard)
+ * or FEC ethernet (10/100 on daughterboard)
+ */
+#if 1
+#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
+#undef CONFIG_FEC_ENET /* disable FEC ethernet */
+#else
+#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
+#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
+#define CFG_DISCOVER_PHY
+#endif
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_EEPROM)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=>" /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x00100000
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFF000000
+#define CFG_IMMR_SIZE ((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+
+#define CFG_FLASH_BASE 0x2800000
+
+#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
+
+#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_HWINFO_LEN 0x0040 /* Length of HW Info Data */
+#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
+
+#if 0
+#define CFG_HWINFO_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN)
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x00040000
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
+ PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently. Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register. For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+#define BCSR_ADDR ((uint) 0xFF01000)
+#define BCSR_SIZE ((uint)(64 * 1024))
+
+#define FLASH_BASE0_PRELIM 0x2800000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */
+
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
+#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+
+#ifdef USE_REAL_FLASH_VALUES
+/*
+ * These values fit our FADS860T ...
+ * The "default" behaviour with 1Mbyte initial doesn't work for us!
+ */
+#define CFG_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */
+#define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */
+#else
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#endif
+
+/* BCSRx - Board Control and Status Registers */
+#define CFG_OR1_REMAP CFG_OR0_REMAP
+#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
+#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+#define CFG_MAMR 0x13a01114
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+
+/* values according to the manual */
+
+
+#define PCMCIA_MEM_ADDR ((uint)0xff020000)
+#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
+
+#define BCSR0 ((uint) (BCSR_ADDR + 00))
+#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
+#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
+#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
+#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
+
+/* FADS bitvalues by Helmut Buchsbaum
+ * see MPC8xxADS User's Manual for a proper description
+ * of the following structures
+ */
+
+#define BCSR0_ERB ((uint)0x80000000)
+#define BCSR0_IP ((uint)0x40000000)
+#define BCSR0_BDIS ((uint)0x10000000)
+#define BCSR0_BPS_MASK ((uint)0x0C000000)
+#define BCSR0_ISB_MASK ((uint)0x01800000)
+#define BCSR0_DBGC_MASK ((uint)0x00600000)
+#define BCSR0_DBPC_MASK ((uint)0x00180000)
+#define BCSR0_EBDF_MASK ((uint)0x00060000)
+
+#define BCSR1_FLASH_EN ((uint)0x80000000)
+#define BCSR1_DRAM_EN ((uint)0x40000000)
+#define BCSR1_ETHEN ((uint)0x20000000)
+#define BCSR1_IRDEN ((uint)0x10000000)
+#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
+#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
+#define BCSR1_BCSR_EN ((uint)0x02000000)
+#define BCSR1_RS232EN_1 ((uint)0x01000000)
+#define BCSR1_PCCEN ((uint)0x00800000)
+#define BCSR1_PCCVCC0 ((uint)0x00400000)
+#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
+#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
+#define BCSR1_RS232EN_2 ((uint)0x00040000)
+#define BCSR1_SDRAM_EN ((uint)0x00020000)
+#define BCSR1_PCCVCC1 ((uint)0x00010000)
+
+#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
+#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
+#define BCSR2_DRAM_PD_SHIFT (23)
+#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
+#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
+
+#define BCSR3_DBID_MASK ((ushort)0x3800)
+#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
+#define BCSR3_BREVNR0 ((ushort)0x0080)
+#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
+#define BCSR3_BREVN1 ((ushort)0x0008)
+#define BCSR3_BREVN2_MASK ((ushort)0x0003)
+
+#define BCSR4_ETHLOOP ((uint)0x80000000)
+#define BCSR4_TFPLDL ((uint)0x40000000)
+#define BCSR4_TPSQEL ((uint)0x20000000)
+#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_EN ((uint)0x08000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860SAR
+#define BCSR4_UTOPIA_EN ((uint)0x08000000)
+#endif /* CONFIG_MPC860SAR */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETH_EN ((uint)0x08000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_SPEED ((uint)0x04000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHCFG0 ((uint)0x04000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VCCO ((uint)0x02000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHFDE ((uint)0x02000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VIDEO_ON ((uint)0x00800000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC823
+#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHCFG1 ((uint)0x00400000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VIDEO_RST ((uint)0x00200000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHRST ((uint)0x00200000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_MODEM_EN ((uint)0x00100000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC823
+#define BCSR4_DATA_VOICE ((uint)0x00080000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC850
+#define BCSR4_DATA_VOICE ((uint)0x00080000)
+#endif /* CONFIG_MPC50 */
+
+#define CONFIG_DRAM_50MHZ 1
+#define CONFIG_SDRAM_50MHZ
+
+#ifdef CONFIG_MPC860T
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
+
+#endif /* CONFIG_MPC860T */
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS 0
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+
+/* PCMCIA configuration */
+
+#define PCMCIA_MAX_SLOTS 2
+
+#ifdef CONFIG_MPC860
+#define PCMCIA_SLOT_A 1
+#endif
+
+#define CFG_BOARD_CONFIG 1
+
+#define CFG_BCSR1_SET 0 /* no bits to set to 1 */
+/* NOTE - These are low to enable (but we use the names in the FADS manual) */
+#define CFG_BCSR1_CLEAR (BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN)
+
+#ifdef CONFIG_SCC1_ENET
+#define CFG_BCSR4_SET (BCSR4_TFPLDL | BCSR4_TPSQEL)
+#define CFG_BCSR4_CLEAR (BCSR4_ETHLOOP)
+#elif defined(CONFIG_FEC_ENET)
+#define CFG_BCSR4_SET (BCSR4_FETHCFG0 | BCSR4_FETHFDE | BCSR4_FETHRST)
+#define CFG_BCSR4_CLEAR (BCSR4_FETH_EN | BCSR4_FETHCFG1)
+#endif
+
+#undef CONFIG_BOOTDELAY
+#undef CONFIG_BOOTCOMMAND
+#undef CONFIG_BOOTARGS
+
+#define CFG_LONGHELP /* undef to save a little memory */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND "bootm 2880000 2900000" /* autoboot command */
+#define CONFIG_BOOTARGS "root=/dev/ram ip=10.1.0.147:::255.128.0.0:fads::off"
+
+#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
+#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
+#define CFG_DISCOVER_PHY
+
+#if 1
+// overrides to put environment in EEROM
+#undef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_OFFSET
+#undef CFG_ENV_SIZE
+#undef CFG_ENV_SECT_SIZE
+
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_OFFSET 0 /* Start right at beginning of NVRAM */
+#define CFG_ENV_SIZE 512 /* Use only a part of it*/
+#define CONFIG_I2C_X 1 /* EEPROM uses 16-bit address */
+
+/* Atmel 24C64 has 32-byte page write mode using last 5 bits of the address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 5
+
+#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */
+#endif
+
+#endif /* __CONFIG_H */
int checkflash (void);
int checkdram (void);
char * strmhz(char *buf, long hz);
-#if defined(CONFIG_COGENT)
-int misc_init_f (void);
-void misc_init_r (bd_t *);
-#endif /* CONFIG_COGENT */
/* common/cmd_bootm.c */
void print_image_hdr (image_header_t *hdr);
void pciinfo (int);
#endif
+#if defined(CONFIG_COGENT) || defined(CONFIG_SXNI855T)
+/* cogent - $(BOARD)/mb.c */
+/* SXNI855T - $(BOARD)/$(BOARD).c */
+int misc_init_f (void);
+void misc_init_r (bd_t *);
+#endif
+
#if defined(CONFIG_SPD823TS) || defined(CONFIG_IVMS8) || defined(CONFIG_IP860)
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
#endif
-#if defined(CONFIG_IP860)
+#if defined(CONFIG_IP860) || (CONFIG_SXNI855T)
/* $(BOARD)/eeprom.c */
void eeprom_init (void);
void eeprom_read (unsigned offset, uchar *buffer, unsigned cnt);
projects / users / rw / ppcboot.git / commitdiff