]> www.infradead.org Git - users/willy/pagecache.git/commitdiff
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi.git
authorStephen Rothwell <sfr@canb.auug.org.au>
Mon, 17 Mar 2025 07:43:05 +0000 (18:43 +1100)
committerStephen Rothwell <sfr@canb.auug.org.au>
Mon, 17 Mar 2025 07:43:05 +0000 (18:43 +1100)
# Conflicts:
# arch/arm64/boot/dts/rockchip/rk3576.dtsi
# drivers/scsi/scsi_debug.c

1  2 
Documentation/userspace-api/ioctl/ioctl-number.rst
MAINTAINERS
arch/arm64/boot/dts/rockchip/rk3576.dtsi
drivers/scsi/lpfc/lpfc_init.c
drivers/scsi/scsi_debug.c
drivers/ufs/host/ufs-exynos.c
drivers/ufs/host/ufs-qcom.c

diff --cc MAINTAINERS
Simple merge
index b379e462294762bac9db0840d58334fbd6a9cf4d,bd55bd8a67cbd018f5a2b09aff1b89d8ca5cff0a..ebb5fc8bb8b1363127b9d3782801c4a79b678a92
                        };
                };
  
+               ufshc: ufshc@2a2d0000 {
+                       compatible = "rockchip,rk3576-ufshc";
+                       reg = <0x0 0x2a2d0000 0x0 0x10000>,
+                             <0x0 0x2b040000 0x0 0x10000>,
+                             <0x0 0x2601f000 0x0 0x1000>,
+                             <0x0 0x2603c000 0x0 0x1000>,
+                             <0x0 0x2a2e0000 0x0 0x10000>;
+                       reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb";
+                       clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>,
+                                <&cru CLK_REF_UFS_CLKOUT>;
+                       clock-names = "core", "pclk", "pclk_mphy", "ref_out";
+                       assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
+                       assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
+                       interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&power RK3576_PD_USB>;
+                       pinctrl-0 = <&ufs_refclk>;
+                       pinctrl-names = "default";
+                       resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>,
+                                <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>;
+                       reset-names = "biu", "sys", "ufs", "grf";
+                       reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
+                       status = "disabled";
+               };
 +              sfc1: spi@2a300000 {
 +                      compatible = "rockchip,sfc";
 +                      reg = <0x0 0x2a300000 0x0 0x4000>;
 +                      interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
 +                      clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>;
 +                      clock-names = "clk_sfc", "hclk_sfc";
 +                      #address-cells = <1>;
 +                      #size-cells = <0>;
 +                      status = "disabled";
 +              };
 +
                sdmmc: mmc@2a310000 {
                        compatible = "rockchip,rk3576-dw-mshc";
                        reg = <0x0 0x2a310000 0x0 0x4000>;
Simple merge
index fe5c30bb263986727b4d943d43a28ee208cb6aae,523f054912e1477102dcb83a7abc42d43d34ecbb..f0eec4708ddd474e7cb95803b77061fc0adff6f3
@@@ -8701,8 -9351,12 +9351,12 @@@ err_out
  static int sdebug_init_cmd_priv(struct Scsi_Host *shost, struct scsi_cmnd *cmd)
  {
        struct sdebug_scsi_cmd *sdsc = scsi_cmd_priv(cmd);
+       struct sdebug_defer *sd_dp = &sdsc->sd_dp;
  
        spin_lock_init(&sdsc->lock);
 -      hrtimer_init(&sd_dp->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED);
 -      sd_dp->hrt.function = sdebug_q_cmd_hrt_complete;
++      hrtimer_setup(&sd_dp->hrt, sdebug_q_cmd_hrt_complete, CLOCK_MONOTONIC,
++                    HRTIMER_MODE_REL_PINNED);
+       INIT_WORK(&sd_dp->ew.work, sdebug_q_cmd_wq_complete);
  
        return 0;
  }
Simple merge
Simple merge