drm/amd/display: fix regamma programming

When new coefficients match cached we would skip setting regamma mode
Also, when doing a stream update we would program regamma for all pipes,
even thos that are not yet powered on. This resulted in never setting
regamma since we would cache before the pipe is powered.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f3397ff173452686405178a515c7906d86bed467..e59e7028ad5795ba05614a5fd285398c92cf90cf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1382,27 +1382,19 @@ static void commit_planes_for_stream(struct dc *dc,
                }
        }
 
-       if (update_type > UPDATE_TYPE_FAST) {
+       if (stream && stream_update && update_type > UPDATE_TYPE_FAST)
                for (j = 0; j < dc->res_pool->pipe_count; j++) {
                        struct pipe_ctx *pipe_ctx =
                                        &context->res_ctx.pipe_ctx[j];
 
-                       if (!pipe_ctx->stream)
+                       if (pipe_ctx->stream != stream)
                                continue;
 
-                       if (stream_update != NULL &&
-                               stream_update->out_transfer_func != NULL) {
-                               dc->hwss.set_output_transfer_func(
-                                               pipe_ctx, pipe_ctx->stream);
-                       }
-
-                       if (stream_update != NULL &&
-                               stream_update->hdr_static_metadata) {
+                       if (stream_update->hdr_static_metadata) {
                                resource_build_info_frame(pipe_ctx);
                                dc->hwss.update_info_frame(pipe_ctx);
                        }
                }
-       }
 }
 
 void dc_commit_updates_for_stream(struct dc *dc,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 21eba82aba97517375765d657c67a523ca37f672..bbf93c94a97762077bc4b37c32a5e25b51768e79 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -188,9 +188,7 @@ static void dpp1_cm_set_regamma_pwl(
        struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
 {
        struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-       uint32_t re_mode = 0;
-       uint32_t obuf_bypass = 0; /* need for pipe split */
-       uint32_t obuf_hupscale = 0;
+       uint32_t re_mode;
 
        switch (mode) {
        case OPP_REGAMMA_BYPASS:
@@ -203,8 +201,9 @@ static void dpp1_cm_set_regamma_pwl(
                re_mode = 2;
                break;
        case OPP_REGAMMA_USER:
+               re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;
                if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
-                       return;
+                       break;
 
                dpp1_cm_power_on_regamma_lut(dpp_base, true);
                dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
@@ -225,9 +224,6 @@ static void dpp1_cm_set_regamma_pwl(
                break;
        }
        REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
-       REG_UPDATE_2(OBUF_CONTROL,
-                       OBUF_BYPASS, obuf_bypass,
-                       OBUF_H_2X_UPSCALE_EN, obuf_hupscale);
 }
 
 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 4355cc21b111bd5d84d5baeb7e3177ebf0e15f8c..ad71fb50f8a51793c6673c0f3e3a4d4d3a421570 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -71,7 +71,6 @@
        SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
        SRI(RECOUT_START, DSCL, id), \
        SRI(RECOUT_SIZE, DSCL, id), \
-       SRI(OBUF_CONTROL, DSCL, id), \
        SRI(CM_ICSC_CONTROL, CM, id), \
        SRI(CM_ICSC_C11_C12, CM, id), \
        SRI(CM_ICSC_C33_C34, CM, id), \
@@ -236,7 +235,6 @@
        TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
        TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
        TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
-       TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
        TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
        TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
        TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
@@ -394,7 +392,6 @@
        TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
        TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
        TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
-       TF_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \
        TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
        TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
        TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
@@ -558,8 +555,6 @@
        type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
        type CM_RGAM_LUT_MODE; \
        type CM_CMOUT_ROUND_TRUNC_MODE; \
-       type OBUF_BYPASS; \
-       type OBUF_H_2X_UPSCALE_EN; \
        type CM_BLNDGAM_LUT_MODE; \
        type CM_BLNDGAM_RAMB_EXP_REGION_START_B; \
        type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
@@ -1096,7 +1091,6 @@ struct dcn_dpp_registers {
        uint32_t CM_RGAM_RAMA_REGION_32_33;
        uint32_t CM_RGAM_CONTROL;
        uint32_t CM_CMOUT_CONTROL;
-       uint32_t OBUF_CONTROL;
        uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK;
        uint32_t CM_BLNDGAM_CONTROL;
        uint32_t CM_BLNDGAM_RAMB_START_CNTL_B;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 99f478c52421a085a24c8550a7d36ed1355fb205..26452b6b38dde5554ff39692d610ec29cbc04154 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -820,7 +820,6 @@ static void reset_hw_ctx_wrap(
                        struct clock_source *old_clk = pipe_ctx_old->clock_source;
 
                        reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
-
                        if (old_clk)
                                old_clk->funcs->cs_power_down(old_clk);
                }