wifi: ath9k: fix AR9003 mac hardware hang check register offset calculation

Fix ath9k_hw_verify_hang()/ar9003_hw_detect_mac_hang() register offset
calculation (do not overflow the shift for the second register/queues
above five, use the register layout described in the comments above
ath9k_hw_verify_hang() instead).

Fixes: 222e04830ff0 ("ath9k: Fix MAC HW hang check for AR9003")
Reported-by: Gregg Wonderly <greggwonderly@seqtechllc.com>
Link: https://lore.kernel.org/linux-wireless/E3A9C354-0CB7-420C-ADEF-F0177FB722F4@seqtechllc.com/
Signed-off-by: Peter Seiderer <ps.report@gmx.net>
Acked-by: Toke Høiland-Jørgensen <toke@toke.dk>
Reviewed-by: Simon Horman <simon.horman@corigine.com>
Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/20230422212423.26065-1-ps.report@gmx.net

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 4f27a9fb1482bf2bc82835e182423d6d5133c685..e9bd13eeee92fd89edab2ce46f9b3bb77fe16721 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -1099,17 +1099,22 @@ static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue)
 {
        u32 dma_dbg_chain, dma_dbg_complete;
        u8 dcu_chain_state, dcu_complete_state;
+       unsigned int dbg_reg, reg_offset;
        int i;
 
-       for (i = 0; i < NUM_STATUS_READS; i++) {
-               if (queue < 6)
-                       dma_dbg_chain = REG_READ(ah, AR_DMADBG_4);
-               else
-                       dma_dbg_chain = REG_READ(ah, AR_DMADBG_5);
+       if (queue < 6) {
+               dbg_reg = AR_DMADBG_4;
+               reg_offset = queue * 5;
+       } else {
+               dbg_reg = AR_DMADBG_5;
+               reg_offset = (queue - 6) * 5;
+       }
 
+       for (i = 0; i < NUM_STATUS_READS; i++) {
+               dma_dbg_chain = REG_READ(ah, dbg_reg);
                dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);
 
-               dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f;
+               dcu_chain_state = (dma_dbg_chain >> reg_offset) & 0x1f;
                dcu_complete_state = dma_dbg_complete & 0x3;
 
                if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))
@@ -1128,6 +1133,7 @@ static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
        u8 dcu_chain_state, dcu_complete_state;
        bool dcu_wait_frdone = false;
        unsigned long chk_dcu = 0;
+       unsigned int reg_offset;
        unsigned int i = 0;
 
        dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
@@ -1139,12 +1145,15 @@ static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
                goto exit;
 
        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
-               if (i < 6)
+               if (i < 6) {
                        chk_dbg = dma_dbg_4;
-               else
+                       reg_offset = i * 5;
+               } else {
                        chk_dbg = dma_dbg_5;
+                       reg_offset = (i - 6) * 5;
+               }
 
-               dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f;
+               dcu_chain_state = (chk_dbg >> reg_offset) & 0x1f;
                if (dcu_chain_state == 0x6) {
                        dcu_wait_frdone = true;
                        chk_dcu |= BIT(i);