set_bit(sdma_queue_id, (unsigned long *)&dqm->sdma_bitmap);
 }
 
-static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
-                               struct qcm_process_device *qpd)
-{
-       uint32_t value = SDMA_ATC;
-
-       if (q->process->is_32bit_user_mode)
-               value |= SDMA_VA_PTR32 | get_sh_mem_bases_32(qpd_to_pdd(qpd));
-       else
-               value |= SDMA_VA_SHARED_BASE(get_sh_mem_bases_nybble_64(
-                                                       qpd_to_pdd(qpd)));
-       q->properties.sdma_vm_addr = value;
-}
-
 static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
                                        struct queue *q,
                                        struct qcm_process_device *qpd)
        pr_debug("     sdma queue id: %d\n", q->properties.sdma_queue_id);
        pr_debug("     sdma engine id: %d\n", q->properties.sdma_engine_id);
 
-       init_sdma_vm(dqm, q, qpd);
+       dqm->ops_asic_specific.init_sdma_vm(dqm, q, qpd);
        retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
                                &q->gart_mqd_addr, &q->properties);
        if (retval != 0) {
 
                                           enum cache_policy alternate_policy,
                                           void __user *alternate_aperture_base,
                                           uint64_t alternate_aperture_size);
+       void    (*init_sdma_vm)(struct device_queue_manager *dqm,
+                               struct queue *q,
+                               struct qcm_process_device *qpd);
 };
 
 /**
 
 static int register_process_cik(struct device_queue_manager *dqm,
                                        struct qcm_process_device *qpd);
 static int initialize_cpsch_cik(struct device_queue_manager *dqm);
+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
+                               struct qcm_process_device *qpd);
 
 void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops)
 {
        ops->set_cache_memory_policy = set_cache_memory_policy_cik;
        ops->register_process = register_process_cik;
        ops->initialize = initialize_cpsch_cik;
+       ops->init_sdma_vm = init_sdma_vm;
 }
 
 static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
        return 0;
 }
 
+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
+                               struct qcm_process_device *qpd)
+{
+       uint32_t value = SDMA_ATC;
+
+       if (q->process->is_32bit_user_mode)
+               value |= SDMA_VA_PTR32 | get_sh_mem_bases_32(qpd_to_pdd(qpd));
+       else
+               value |= SDMA_VA_SHARED_BASE(get_sh_mem_bases_nybble_64(
+                                                       qpd_to_pdd(qpd)));
+       q->properties.sdma_vm_addr = value;
+}
+
 static int initialize_cpsch_cik(struct device_queue_manager *dqm)
 {
        return init_pipelines(dqm, get_pipes_num(dqm), get_first_pipe(dqm));
 
 static int register_process_vi(struct device_queue_manager *dqm,
                                        struct qcm_process_device *qpd);
 static int initialize_cpsch_vi(struct device_queue_manager *dqm);
+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
+                               struct qcm_process_device *qpd);
 
 void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops)
 {
        ops->set_cache_memory_policy = set_cache_memory_policy_vi;
        ops->register_process = register_process_vi;
        ops->initialize = initialize_cpsch_vi;
+       ops->init_sdma_vm = init_sdma_vm;
 }
 
 static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
        return -1;
 }
 
+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
+                               struct qcm_process_device *qpd)
+{
+}
+
 static int initialize_cpsch_vi(struct device_queue_manager *dqm)
 {
        return 0;