arm64: entry: cleanup sp_el0 manipulation

The kernel stashes the current task struct in sp_el0 so that this can be
acquired consistently/cheaply when required. When we take an exception
from EL0 we have to:

1) stash the original sp_el0 value
2) find the current task
3) update sp_el0 with the current task pointer

Currently steps #1 and #2 occur in one place, and step #3 a while later.
As the value of sp_el0 is immaterial between these points, let's move
them together to make the code clearer and minimize ifdeffery. This
necessitates moving the comment for MDSCR_EL1.SS.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 7c6a0a41676f83ce0f40cfc1e3197a03e6ca3570..3d7a9c0ab8440ed1da3082be09633c0bb60f2b85 100644 (file)
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -167,9 +167,13 @@ alternative_cb_end
        .if     \el == 0
        clear_gp_regs
        mrs     x21, sp_el0
-       ldr_this_cpu    tsk, __entry_task, x20  // Ensure MDSCR_EL1.SS is clear,
-       ldr     x19, [tsk, #TSK_TI_FLAGS]       // since we can unmask debug
-       disable_step_tsk x19, x20               // exceptions when scheduling.
+       ldr_this_cpu    tsk, __entry_task, x20
+       msr     sp_el0, tsk
+
+       // Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions
+       // when scheduling.
+       ldr     x19, [tsk, #TSK_TI_FLAGS]
+       disable_step_tsk x19, x20
 
        apply_ssbd 1, x22, x23
 
@@ -232,13 +236,6 @@ alternative_else_nop_endif
        str     w21, [sp, #S_SYSCALLNO]
        .endif
 
-       /*
-        * Set sp_el0 to current thread_info.
-        */
-       .if     \el == 0
-       msr     sp_el0, tsk
-       .endif
-
        /* Save pmr */
 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
        mrs_s   x20, SYS_ICC_PMR_EL1