Modifications for 1.0.6:
======================================================================
+* Remove references to obsolete CFG_HWINFO_LEN stuff
+
+* Work around problem with transmit of 1st eth packet on AMX
+
* Fixed "clocks_in_mhz" typo
======================================================================
}
/* Remap FLASH according to real size */
- memctl->memc_or0 = CFG_OR0_PRELIM;
- memctl->memc_br0 = CFG_BR0_PRELIM;
+ memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+ memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
/* Re-do sizing to get full correct info */
size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
#include <config.h>
#include "mpc8xx.h"
-/*
+/*
* Memory Controller Using
*
* CS0 - Flash memory (0x40000000)
/* ------------------------------------------------------------------------- */
-#define _NOT_USED_ 0xFFFFFFFF
-
-#if defined(CONFIG_ICU862)
/* 40x2MHz tables */
-const uint sdram[]=
+const uint sdram_table[]=
{ 0x0e06fc04, 0x11acfc04, 0xefa98c00, 0x1ff77c47,
0xeeeabc35, 0x11b57fff, 0xffffffff, 0xffffffff,
0x0e06fc04, 0x10adfc00, 0xf0affc00, 0xf0affc00,
0xe1bbfc00, 0x1ff77c47, 0xffffffff, 0xffffffff,
+#if 0
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+#else
+ 0xffffffff, 0xeffbbc04, 0x1ff77c34, 0xefeabc34,
+ 0x1fb57c35, 0xffffffff, 0xffffffff, 0xffffffff,
+#endif
0x0e26bc04, 0x01b93c00, 0x1ff77c47, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x0e06bc04, 0x10ad7c00, 0xf0affc00, 0xf0affc00,
0xf1b5fc07, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0xfffffc07, 0xffffffff, 0xffffffff, 0xffffffff };
-#endif
#define MAMR_VALUE 0x27904111
#define MCR_INIT 0x8000222f
}
/* ------------------------------------------------------------------------- */
-int _draminit(uint base, uint noMbytes, uint edo, uint delay)
-{
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-void _dramdisable(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_br2 = 0x00000000;
- memctl->memc_br3 = 0x00000000;
-
- /* maybe we should turn off upma here or something */
-}
-int _initsdram(uint base, uint noMbytes)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- if(noMbytes != 32)
- {
- return -1;
- }
-
- upmconfig(UPMA, (uint *)sdram,sizeof(sdram)/sizeof(uint));
-
-
- /* Configure the refresh (mostly). This needs to be
- * based upon processor clock speed and optimized to provide
- * the highest level of performance. For multiple banks,
- * this time has to be divided by the number of banks.
- * Although it is not clear anywhere, it appears the
- * refresh steps through the chip selects for this UPM
- * on each refresh cycle.
- * We have to be careful changing
- * UPM registers after we ask it to run these commands.
- */
-
- memctl->memc_mamr = MAMR_VALUE;
- memctl->memc_mcr = MCR_INIT;
- memctl->memc_mar = MAR_VALUE;
- memctl->memc_mcr = MCR_L_M_R;
-
- memctl->memc_mptpr = MPTPR_VALUE;
-
- udelay(200);
-
- memctl->memc_or1 = OR1_VALUE;
- memctl->memc_br1 = BR1_VALUE | base;
-
- return 0;
-}
+static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
-void _sdramdisable(void)
+long int initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_br1 = 0x00000000;
-
- /* maybe we should turn off upmb here or something */
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size8, size9;
+ long int size_b0 = 0;
+ unsigned long reg;
+
+ upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller bank 1 to the SDRAM bank at
+ * preliminary address - these have to be modified after the
+ * SDRAM size has been determined.
+ */
+ memctl->memc_or1 = CFG_OR1_PRELIM;
+ memctl->memc_br1 = CFG_BR1_PRELIM;
+
+ memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+
+ udelay(200);
+
+ /* perform SDRAM initializsation sequence */
+
+ memctl->memc_mcr = 0x80002111; /* SDRAM bank 0 */
+ udelay(1);
+ memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
+ udelay(1);
+
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+ udelay (1000);
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ * try 8 column mode
+ */
+ size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+
+ udelay (1000);
+
+ /*
+ * try 9 column mode
+ */
+ size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+
+ if (size8 < size9) { /* leave configuration at 9 columns */
+ size_b0 = size9;
+/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
+ } else { /* back to 8 columns */
+ size_b0 = size8;
+ memctl->memc_mamr = CFG_MAMR_8COL;
+ udelay(500);
+/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
+ }
+
+ udelay (1000);
+
+ /*
+ * Adjust refresh rate depending on SDRAM type, both banks
+ * For types > 128 MBit leave it at the current (fast) rate
+ */
+ if ((size_b0 < 0x02000000)) {
+ /* reduce to 15.6 us (62.4 us / quad) */
+ memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+ udelay(1000);
+ }
+
+ /*
+ * Final mapping
+ */
+
+ memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+ /* adjust refresh rate depending on SDRAM type, one bank */
+ reg = memctl->memc_mptpr;
+ reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
+ memctl->memc_mptpr = reg;
+
+ udelay(10000);
+
+ return (size_b0);
}
/* ------------------------------------------------------------------------- */
-int initsdram(uint base, uint *noMbytes)
-{
- uint m = 32;
-
- *noMbytes = m;
-
- if(!_initsdram(base, m))
- {
-
- return 0;
- }
- else
- {
- _sdramdisable();
-
- return -1;
- }
- return 0;
-}
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
-long int initdram (int board_type)
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
- uint m;
-
- if (!initsdram(0x00000000, &m)) {
- printf("(%u MB SDRAM) ", m);
- } else {
-
- /********************************
- *DRAM ERROR, HALT PROCESSOR
- *********************************/
- while(1);
-
- return -1;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile long int *addr;
+ ulong cnt, val;
+ ulong save[32]; /* to make test non-destructive */
+ unsigned char i = 0;
+
+ memctl->memc_mamr = mamr_value;
+
+ for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ save[i++] = *addr;
+ *addr = ~cnt;
+ }
+
+ /* write 0 to base address */
+ addr = base;
+ save[i] = *addr;
+ *addr = 0;
+
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ *addr = save[i];
+ return (0);
+ }
+
+ for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+ val = *addr;
+ *addr = save[--i];
+
+ if (val != (~cnt)) {
+ return (cnt * sizeof(long));
}
-
- return (m << 20);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
+ }
+ return (maxsize);
}
-
* First reserve memory for monitor code at end of DRAM.
*/
len = get_endaddr() - CFG_MONITOR_BASE;
-
+
if (len > CFG_MONITOR_LEN) {
printf ("*** PPCBoot size %ld > reserved memory (%d)\n",
len, CFG_MONITOR_LEN);
#include <mpc8xx.h>
#include <asm/cache.h>
-#if (defined(CONFIG_MPC860) || defined(CONFIG_MPC855))
+#if ((defined(CONFIG_MPC860) || defined(CONFIG_MPC855)) && \
+ !defined(CONFIG_MPC862))
# ifdef CONFIG_MPC855
# define ID_STR "PC855"
# else
return 0;
}
+#elif defined(CONFIG_MPC862)
+
+static int check_CPU(long clock, uint pvr, uint immr)
+{
+ volatile immap_t *immap = (immap_t *)(immr & 0xFFFF0000);
+ uint k, m;
+ char buf[32];
+ char pre = 'X';
+ char *mid = "xx";
+ char *suf;
+
+ /* the highest 16 bits should be 0x0050 for a 8xx */
+
+ if((pvr >> 16) != 0x0050)
+ return -1;
+
+ k = (immr << 16) | *((ushort *) &immap->im_cpm.cp_dparam[0xB0]);
+ m = 0;
+
+ switch(k) {
+
+ /* this value is not documented anywhere */
+ case 0x06000000 : mid = "P"; suf = "0"; break;
+ default: suf = NULL; break;
+ }
+
+ if (suf)
+ printf ("%cPC862%sZPnn%s", pre, mid, suf);
+ else
+ printf ("unknown MPC862 (0x%08x)", k);
+
+ printf(" at %s MHz:", strmhz(buf, clock));
+
+ printf(" %u kB I-Cache", checkicache() >> 10);
+ printf(" %u kB D-Cache", checkdcache() >> 10);
+
+ /* lets check and see if we're running on a 862T (or P?) */
+
+ immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
+ if(immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
+ printf(" FEC present");
+ }
+
+ if(!m) {
+ printf("\n *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***");
+ }
+
+ printf("\n");
+
+ return 0;
+}
+
#elif defined(CONFIG_MPC823)
static int check_CPU(long clock, uint pvr, uint immr)
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-#ifdef CONFIG_FADS /* Trying to work around FADS problem with first packet */
+ /*
+ * Work around transmit problem with first eth packet
+ */
+#if defined (CONFIG_FADS)
udelay(10000); /* wait 10 ms */
+#elif defined (CONFIG_AMX860)
+ udelay(100000); /* wait 100 ms */
#endif
return 1;
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_HWINFO_LEN 0x0040 /* Length of HW Info Data */
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
/*
#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_HWINFO_LEN 0x0040 /* Length of HW Info Data */
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
-#if 0
-#define CFG_HWINFO_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN)
-#endif
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_HWINFO_LEN 0x0040 /* Length of HW Info Data */
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
/*
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <mpc8xx_irq.h>
+
/*
* High Level Configuration Options
* (easy to change)
*/
-#include <mpc8xx_irq.h>
-
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_ICU862 1
#define CONFIG_BAUDRATE 9600
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#if 0
-#define MPC8XX_FACT 10 /* Multiply by 10 */
-#define MPC8XX_XIN 5000000 /* 5 MHz in */
-#else
+#if 1 /* for 50MHz version of processor */
+#define MPC8XX_FACT 12 /* Multiply by 12 */
+#define MPC8XX_XIN 4000000 /* 4 MHz in */
+#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */
+#else /* for 80MHz version of processor */
#define MPC8XX_FACT 20 /* Multiply by 20 */
#define MPC8XX_XIN 4000000 /* 4 MHz in */
-#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
-#endif
-
#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */
+#endif
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
+ "bootp;" \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
"bootm"
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-/* choose SCC1 ethernet (10BASET on motherboard)
- * or FEC ethernet (10/100 on daughterboard)
- */
-#if 0
-#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
-#undef CONFIG_FEC_ENET /* disable FEC ethernet */
-#else
#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
#if 0
#else
#undef CFG_DISCOVER_PHY
#endif
-#endif
-#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
-#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
-#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */
#endif
#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_HWINFO_LEN 0x0040 /* Length of HW Info Data */
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
/*
/*
* Init Memory Controller:
*
- * BR0/1 and OR0/1 (FLASH)
+ * BR0 and OR0 (FLASH)
*/
-/* the other CS:s are determined by looking at parameters in BCSRx */
-
-#define BCSR_ADDR ((uint) 0xFF010000)
-#define BCSR_SIZE ((uint)(64 * 1024))
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */
+#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */
-#define CFG_REMAP_OR_AM 0xFF000000 /* OR addr mask */
-#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
-#define USE_REAL_FLASH_VALUES 1
+#define CFG_OR0_PRELIM 0xFF000954 /* Real values for the board */
+#define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */
-#ifdef USE_REAL_FLASH_VALUES
/*
- * These values fit our FADS860T ...
- * The "default" behaviour with 1Mbyte initial doesn't work for us!
+ * BR1 and OR1 (SDRAM)
*/
-#define CFG_OR0_PRELIM 0xFF000954 /* Real values for the board */
-#define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */
-#else
-#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
-#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-#endif
+#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */
+#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-#if 0
-/* BCSRx - Board Control and Status Registers */
-#define CFG_OR1_REMAP CFG_OR0_REMAP
-#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
-#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
-#endif
+#define CFG_OR_TIMING_SDRAM 0x00000900 /* BIH is set */
+#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
+#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
/*
* Memory Periodic Timer Prescaler
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/* values according to the manual */
-
-
-#define PCMCIA_MEM_ADDR ((uint)0xff020000)
-#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
-
-#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_SDRAM_50MHZ
-
#ifdef CONFIG_MPC860T
/* Interrupt level assignments.
#endif /* CONFIG_MPC860T */
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS 0
-
-/* Machine type
-*/
-#define _MACH_8xx (_MACH_fads)
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-
-/* PCMCIA configuration */
-
-#define PCMCIA_MAX_SLOTS 2
-
-#ifdef CONFIG_MPC860
-#define PCMCIA_SLOT_A 1
-#endif
#endif /* __CONFIG_H */
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CFG_HWINFO_LEN 0x0040 /* Length of HW Info Data */
#define CFG_HWINFO_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN)
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_HWINFO_LEN 0x0040 /* Length of HW Info Data */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#if 0
-#define CFG_HWINFO_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN)
-#endif
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
projects / users / rw / ppcboot.git / commitdiff