net: hns3: fixed reset failure issues caused by the incorrect reset type

When a reset type that is not supported by the driver is input, a reset
pending flag bit of the HNAE3_NONE_RESET type is generated in
reset_pending. The driver does not have a mechanism to clear this type
of error. As a result, the driver considers that the reset is not
complete. This patch provides a mechanism to clear the
HNAE3_NONE_RESET flag and the parameter of
hnae3_ae_ops.set_default_reset_request is verified.

The error message:
hns3 0000:39:01.0: cmd failed -16
hns3 0000:39:01.0: hclge device re-init failed, VF is disabled!
hns3 0000:39:01.0: failed to reset VF stack
hns3 0000:39:01.0: failed to reset VF(4)
hns3 0000:39:01.0: prepare reset(2) wait done
hns3 0000:39:01.0 eth4: already uninitialized

Use the crash tool to view struct hclgevf_dev:
struct hclgevf_dev {
...
	default_reset_request = 0x20,
	reset_level = HNAE3_NONE_RESET,
	reset_pending = 0x100,
	reset_type = HNAE3_NONE_RESET,
...
};

Fixes: 720bd5837e37 ("net: hns3: add set_default_reset_request in the hnae3_ae_ops")
Signed-off-by: Hao Lan <lanhao@huawei.com>
Signed-off-by: Jijie Shao <shaojijie@huawei.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index bd86efd92a5a7d0eb92b97b82b5e03dc875d1049..35c618c794bec510a2424d40206bad00c5709a5e 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -3584,6 +3584,17 @@ static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,
        return ret;
 }
 
+static void hclge_set_reset_pending(struct hclge_dev *hdev,
+                                   enum hnae3_reset_type reset_type)
+{
+       /* When an incorrect reset type is executed, the get_reset_level
+        * function generates the HNAE3_NONE_RESET flag. As a result, this
+        * type do not need to pending.
+        */
+       if (reset_type != HNAE3_NONE_RESET)
+               set_bit(reset_type, &hdev->reset_pending);
+}
+
 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
 {
        u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg;
@@ -3604,7 +3615,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
         */
        if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) {
                dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
-               set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
+               hclge_set_reset_pending(hdev, HNAE3_IMP_RESET);
                set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
                *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
                hdev->rst_stats.imp_rst_cnt++;
@@ -3614,7 +3625,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
        if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) {
                dev_info(&hdev->pdev->dev, "global reset interrupt\n");
                set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
-               set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
+               hclge_set_reset_pending(hdev, HNAE3_GLOBAL_RESET);
                *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
                hdev->rst_stats.global_rst_cnt++;
                return HCLGE_VECTOR0_EVENT_RST;
@@ -4062,7 +4073,7 @@ static void hclge_do_reset(struct hclge_dev *hdev)
        case HNAE3_FUNC_RESET:
                dev_info(&pdev->dev, "PF reset requested\n");
                /* schedule again to check later */
-               set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
+               hclge_set_reset_pending(hdev, HNAE3_FUNC_RESET);
                hclge_reset_task_schedule(hdev);
                break;
        default:
@@ -4096,6 +4107,8 @@ static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
                clear_bit(HNAE3_FLR_RESET, addr);
        }
 
+       clear_bit(HNAE3_NONE_RESET, addr);
+
        if (hdev->reset_type != HNAE3_NONE_RESET &&
            rst_level < hdev->reset_type)
                return HNAE3_NONE_RESET;
@@ -4237,7 +4250,7 @@ static bool hclge_reset_err_handle(struct hclge_dev *hdev)
                return false;
        } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) {
                hdev->rst_stats.reset_fail_cnt++;
-               set_bit(hdev->reset_type, &hdev->reset_pending);
+               hclge_set_reset_pending(hdev, hdev->reset_type);
                dev_info(&hdev->pdev->dev,
                         "re-schedule reset task(%u)\n",
                         hdev->rst_stats.reset_fail_cnt);
@@ -4480,8 +4493,20 @@ static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
                                        enum hnae3_reset_type rst_type)
 {
+#define HCLGE_SUPPORT_RESET_TYPE \
+       (BIT(HNAE3_FLR_RESET) | BIT(HNAE3_FUNC_RESET) | \
+       BIT(HNAE3_GLOBAL_RESET) | BIT(HNAE3_IMP_RESET))
+
        struct hclge_dev *hdev = ae_dev->priv;
 
+       if (!(BIT(rst_type) & HCLGE_SUPPORT_RESET_TYPE)) {
+               /* To prevent reset triggered by hclge_reset_event */
+               set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request);
+               dev_warn(&hdev->pdev->dev, "unsupported reset type %d\n",
+                        rst_type);
+               return;
+       }
+
        set_bit(rst_type, &hdev->default_reset_request);
 }
 

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
index 094a7c7b55921f9a0ddb3637ebe8d5ca9eb46c38..ab54e6155e933635c1066e379dd8984b4d0da3e9 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
@@ -1395,6 +1395,17 @@ static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev,
        return ret;
 }
 
+static void hclgevf_set_reset_pending(struct hclgevf_dev *hdev,
+                                     enum hnae3_reset_type reset_type)
+{
+       /* When an incorrect reset type is executed, the get_reset_level
+        * function generates the HNAE3_NONE_RESET flag. As a result, this
+        * type do not need to pending.
+        */
+       if (reset_type != HNAE3_NONE_RESET)
+               set_bit(reset_type, &hdev->reset_pending);
+}
+
 static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
 {
 #define HCLGEVF_RESET_WAIT_US  20000
@@ -1544,7 +1555,7 @@ static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
                hdev->rst_stats.rst_fail_cnt);
 
        if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)
-               set_bit(hdev->reset_type, &hdev->reset_pending);
+               hclgevf_set_reset_pending(hdev, hdev->reset_type);
 
        if (hclgevf_is_reset_pending(hdev)) {
                set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
@@ -1664,6 +1675,8 @@ static enum hnae3_reset_type hclgevf_get_reset_level(unsigned long *addr)
                clear_bit(HNAE3_FLR_RESET, addr);
        }
 
+       clear_bit(HNAE3_NONE_RESET, addr);
+
        return rst_level;
 }
 
@@ -1673,14 +1686,15 @@ static void hclgevf_reset_event(struct pci_dev *pdev,
        struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
        struct hclgevf_dev *hdev = ae_dev->priv;
 
-       dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
-
        if (hdev->default_reset_request)
                hdev->reset_level =
                        hclgevf_get_reset_level(&hdev->default_reset_request);
        else
                hdev->reset_level = HNAE3_VF_FUNC_RESET;
 
+       dev_info(&hdev->pdev->dev, "received reset request from VF enet, reset level is %d\n",
+                hdev->reset_level);
+
        /* reset of this VF requested */
        set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
        hclgevf_reset_task_schedule(hdev);
@@ -1691,8 +1705,20 @@ static void hclgevf_reset_event(struct pci_dev *pdev,
 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
                                          enum hnae3_reset_type rst_type)
 {
+#define HCLGEVF_SUPPORT_RESET_TYPE \
+       (BIT(HNAE3_VF_RESET) | BIT(HNAE3_VF_FUNC_RESET) | \
+       BIT(HNAE3_VF_PF_FUNC_RESET) | BIT(HNAE3_VF_FULL_RESET) | \
+       BIT(HNAE3_FLR_RESET) | BIT(HNAE3_VF_EXP_RESET))
+
        struct hclgevf_dev *hdev = ae_dev->priv;
 
+       if (!(BIT(rst_type) & HCLGEVF_SUPPORT_RESET_TYPE)) {
+               /* To prevent reset triggered by hclge_reset_event */
+               set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request);
+               dev_info(&hdev->pdev->dev, "unsupported reset type %d\n",
+                        rst_type);
+               return;
+       }
        set_bit(rst_type, &hdev->default_reset_request);
 }
 
@@ -1849,14 +1875,14 @@ static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
                 */
                if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {
                        /* prepare for full reset of stack + pcie interface */
-                       set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
+                       hclgevf_set_reset_pending(hdev, HNAE3_VF_FULL_RESET);
 
                        /* "defer" schedule the reset task again */
                        set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
                } else {
                        hdev->reset_attempts++;
 
-                       set_bit(hdev->reset_level, &hdev->reset_pending);
+                       hclgevf_set_reset_pending(hdev, hdev->reset_level);
                        set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
                }
                hclgevf_reset_task_schedule(hdev);
@@ -1979,7 +2005,7 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
                rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
                dev_info(&hdev->pdev->dev,
                         "receive reset interrupt 0x%x!\n", rst_ing_reg);
-               set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
+               hclgevf_set_reset_pending(hdev, HNAE3_VF_RESET);
                set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
                set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
                *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);