drm/amd/display: Enable mem low power control for DCN3.1 sub-IP blocks

[WHY]
Sequences to handle powering down these sub-IP blocks are now ready for use

Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index cf6392eadaf2badb1cb4f69f039f1c92bf848c1f..613d34bde7dd15529e53425b2656933ba71db26b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1009,15 +1009,15 @@ static const struct dc_debug_options debug_defaults_drv = {
        .use_max_lb = true,
        .enable_mem_low_power = {
                .bits = {
-                       .vga = false,
-                       .i2c = false,
+                       .vga = true,
+                       .i2c = true,
                        .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
-                       .dscl = false,
-                       .cm = false,
-                       .mpc = false,
-                       .optc = false,
-                       .vpg = false,
-                       .afmt = false,
+                       .dscl = true,
+                       .cm = true,
+                       .mpc = true,
+                       .optc = true,
+                       .vpg = true,
+                       .afmt = true,
                }
        },
        .optimize_edp_link_rate = true,