drm/amdgpu: support sdma 2~7 doorbell range register offset

Update the doorbell range registers to support additional
SDMA rings.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 2e1098c5c32b39b3f241608c857cf0e8b8890c38..fc45eaeaba6e16a72613d647d89c6abcc7579ed9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -86,10 +86,24 @@ static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
                        bool use_doorbell, int doorbell_index, int doorbell_size)
 {
-       u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
-                       SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
+       u32 reg, doorbell_range;
 
-       u32 doorbell_range = RREG32(reg);
+       if (instance < 2)
+               reg = instance +
+                       SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
+       else
+               /*
+                * These registers address of SDMA2~7 is not consecutive
+                * from SDMA0~1. Need plus 4 dwords offset.
+                *
+                *   BIF_SDMA0_DOORBELL_RANGE:  0x3bc0
+                *   BIF_SDMA1_DOORBELL_RANGE:  0x3bc4
+                *   BIF_SDMA2_DOORBELL_RANGE:  0x3bd8
+                */
+               reg = instance + 0x4 +
+                       SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
+
+       doorbell_range = RREG32(reg);
 
        if (use_doorbell) {
                doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);