u8 val;
 
        val = rtl8723au_read8(padapter, REG_LEDCFG2);
-       /*  Let 8051 take control antenna settting */
+       /*  Let 8051 take control antenna setting */
        val |= BIT(7);          /*  DPDT_SEL_EN, 0x4C[23] */
        rtl8723au_write8(padapter, REG_LEDCFG2, val);
 }
        u8 val;
 
        val = rtl8723au_read8(padapter, REG_LEDCFG2);
-       /*  Let 8051 take control antenna settting */
+       /*  Let 8051 take control antenna setting */
        if (!(val & BIT(7))) {
                val |= BIT(7);  /*  DPDT_SEL_EN, 0x4C[23] */
                rtl8723au_write8(padapter, REG_LEDCFG2, val);
        u8 val;
 
        val = rtl8723au_read8(padapter, REG_LEDCFG2);
-       /*  Let 8051 take control antenna settting */
+       /*  Let 8051 take control antenna setting */
        val &= ~BIT(7);         /*  DPDT_SEL_EN, clear 0x4C[23] */
        rtl8723au_write8(padapter, REG_LEDCFG2, val);
 }
                /*  If we want to SS mode, we can not reset 8051. */
                if ((val8 & BIT(1)) && padapter->bFWReady) {
                        /* IF fw in RAM code, do reset */
-                       /*  2010/08/25 MH Accordign to RD alfred's
+                       /*  2010/08/25 MH According to RD alfred's
                            suggestion, we need to disable other */
                        /*  HRCV INT to influence 8051 reset. */
                        rtl8723au_write8(padapter, REG_FWIMR, 0x20);