drm/msm/adreno: Add A305B support

Add support for the Adreno 305B GPU that is found in MSM8226(v2) SoC.
Previously this was mistakenly claimed to be supported but using wrong
a configuration.

In MSM8226v1 there's also a A305B but with chipid 0x03000510 which
should work with the same configuration but due to lack of hardware for
testing this is not added.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: David Heidelberg <david@ixit.cz>
Patchwork: https://patchwork.freedesktop.org/patch/575274/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index c86b377f6f0d72441d0cd4fe06bd3470659bccf4..5273dc8498381ce09e878894f4eb56263900be39 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -134,6 +134,13 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
                /* Set up AOOO: */
                gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
                gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
+       } else if (adreno_is_a305b(adreno_gpu)) {
+               gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x00181818);
+               gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x00181818);
+               gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000018);
+               gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000018);
+               gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x00000303);
+               gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
        } else if (adreno_is_a306(adreno_gpu)) {
                gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
                gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);
@@ -230,7 +237,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
        gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
 
        /* Enable Clock gating: */
-       if (adreno_is_a306(adreno_gpu))
+       if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu))
                gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
        else if (adreno_is_a320(adreno_gpu))
                gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
@@ -333,7 +340,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
                                AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
                                AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
                                AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(14));
-       } else if (adreno_is_a330(adreno_gpu)) {
+       } else if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) {
                /* NOTE: this (value take from downstream android driver)
                 * includes some bits outside of the known bitfields.  But
                 * A330 has this "MERCIU queue" thing too, which might
@@ -559,7 +566,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
                goto fail;
 
        /* if needed, allocate gmem: */
-       if (adreno_is_a330(adreno_gpu)) {
+       if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) {
                ret = adreno_gpu_ocmem_init(&adreno_gpu->base.pdev->dev,
                                            adreno_gpu, &a3xx_gpu->ocmem);
                if (ret)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index b81f90fb425752aef86bbafa895b4fa2a4cfd40a..ff24bf45eb130ead091e5ff1676b312d8e57ee26 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -55,10 +55,17 @@ static const struct adreno_info gpulist[] = {
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
                .init  = a2xx_gpu_init,
        }, {
-               .chip_ids = ADRENO_CHIP_IDS(
-                       0x03000512,
-                       0x03000520
-               ),
+               .chip_ids = ADRENO_CHIP_IDS(0x03000512),
+               .family = ADRENO_3XX,
+               .fw = {
+                       [ADRENO_FW_PM4] = "a330_pm4.fw",
+                       [ADRENO_FW_PFP] = "a330_pfp.fw",
+               },
+               .gmem  = SZ_128K,
+               .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+               .init  = a3xx_gpu_init,
+       }, {
+               .chip_ids = ADRENO_CHIP_IDS(0x03000520),
                .family = ADRENO_3XX,
                .revn  = 305,
                .fw = {

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index bc14df96feb013a9592c203aab2ab59b7b61e336..d3c41af706df80032f3b6953652905597564830b 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -256,6 +256,11 @@ static inline bool adreno_is_a305(const struct adreno_gpu *gpu)
        return adreno_is_revn(gpu, 305);
 }
 
+static inline bool adreno_is_a305b(const struct adreno_gpu *gpu)
+{
+       return gpu->info->chip_ids[0] == 0x03000512;
+}
+
 static inline bool adreno_is_a306(const struct adreno_gpu *gpu)
 {
        /* yes, 307, because a305c is 306 */