RDSPROTO Patch by Marius Gröger, 2 Apr 2001 14:08:04

diff --git a/board/rsdproto/config.mk b/board/rsdproto/config.mk
index f1f1eb44c5c36e8c7ff4cfc120b79cf9e5455b49..001411da0ffccbfd90504be812ded56043d38fd7 100644 (file)
--- a/board/rsdproto/config.mk
+++ b/board/rsdproto/config.mk
@@ -29,5 +29,5 @@
 # MBX8xx boards
 #
 
-TEXT_BASE = 0xfff00000
+TEXT_BASE = 0xff000000
 //TEXT_BASE  = 0x00200000

diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c
index 6c23843913c6200b08830deac9fe2e577d043618..3917ff16e7653ffdd1ee5aad37b7659f65839a5f 100644 (file)
--- a/board/rsdproto/rsdproto.c
+++ b/board/rsdproto/rsdproto.c
@@ -133,9 +133,9 @@ const iop_conf_t iop_conf_tab[4][32] = {
        /* PC22 */ {   0,   0,   0,   0,   0,   0   },
        /* PC21 */ {   0,   0,   0,   0,   0,   0   },
        /* PC20 */ {   0,   0,   0,   0,   0,   0   },
-       /* PC19 */ {   0,   0,   0,   0,   0,   0   },
+       /* PC19 */ {   1,   1,   0,   0,   0,   0   },
        /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* ETHRXCLK: CLK14 */
-       /* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* ETHTXCLK: CLK15 */
+       /* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* ETHTXCLK: CLK15 */
        /* PC16 */ {   0,   0,   0,   0,   0,   0   },
        /* PC15 */ {   0,   0,   0,   0,   0,   0   },
        /* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART CD/ */

diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c
index 586fe850453935beeb29919050a8c6e57266228f..ec0c917f57bd2d761c187b6655e21f16aa3de7df 100644 (file)
--- a/cpu/mpc8260/ether_fcc.c
+++ b/cpu/mpc8260/ether_fcc.c
@@ -76,13 +76,13 @@
 #if defined(CONFIG_RSD_PROTO)
 /* 
  * Attention: this is board-specific
- * - Rx-CLK is CLK14
- * - Tx-CLK is CLK15
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
  * - Select bus for bd/buffers (see 28-13)
  * - Enable Full Duplex in FSMR
  */
 #define CMXFCR_MASK            (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-#define CMXFCR_VALUE           (CMXFCR_RF2CS_CLK14 | CMXFCR_TF2CS_CLK15)
+#define CMXFCR_VALUE           (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 #define CPMFCR_RAMTYPE         (0)
 #define FCC_PSMR               (FCC_PSMR_FDE | FCC_PSMR_LPB)
 #endif

diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c
index 939bfb62d40c1121c3f6dfa392f2aca586e3d340..75a348e76ca655b42af6b82f3792e02142bbbc99 100644 (file)
--- a/cpu/mpc8xx/i2c.c
+++ b/cpu/mpc8xx/i2c.c
@@ -2,6 +2,9 @@
  * (C) Copyright 2000
  * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
  *
+ * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *

diff --git a/include/config_rsdproto.h b/include/config_rsdproto.h
index d3cebb4f3600a3c39be2dc08d2062cb7edd5d228..e84b6fb0c8efd74aa4b32423429fa5b61d4e5b36 100644 (file)
--- a/include/config_rsdproto.h
+++ b/include/config_rsdproto.h
@@ -82,6 +82,14 @@
 
 #define CONFIG_COMMANDS                (CONFIG_CMD_DFL & ~CFG_CMD_KGDB)
 
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let PPCBoot live at 0x00000000.
+ */
+#define CFG_RSD_BOOT_LOW 1 
+
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
@@ -166,13 +174,26 @@
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  */
+
+#if defined(CFG_RSD_BOOT_LOW)
+#  define  CFG_RSD_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CFG_RSD_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CFG_RSD_BOOT_LOW) */
+
+/* get the HRCW ISB field from CFG_IMMR */
+#define CFG_RSD_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
+                            ((CFG_IMMR & 0x01000000) >> 7)  |\
+                            ((CFG_IMMR & 0x00100000) >> 4) )
+
 #define CFG_HRCW_MASTER        (HRCW_L2CPC10 | \
                         HRCW_DPPC11 | \
-                        HRCW_ISB100 | \
-                HRCW_MMR00 | \
-                HRCW_APPC10 | \
-                HRCW_CS10PC00 | \
-                HRCW_MODCK_H0000)
+                         CFG_RSD_HRCW_IMMR |\
+                        HRCW_MMR00 | \
+                        HRCW_APPC10 | \
+                        HRCW_CS10PC00 | \
+                        HRCW_MODCK_H0000 |\
+                        CFG_RSD_HRCW_BOOT_FLAGS)
 
 /* no slaves */
 #define CFG_HRCW_SLAVE1        0
@@ -199,13 +220,13 @@
  * Note also that the logic that sets CFG_RAMBOOT is platform dependend.
  */
 #define        CFG_SDRAM_BASE          PHYS_SDRAM_60X
-#define CFG_FLASH_BASE         0xFFF00000
+#define CFG_FLASH_BASE         PHYS_FLASH
 //#define      CFG_MONITOR_BASE        0x200000
-#define        CFG_MONITOR_BASE        0xfff00000
+#define        CFG_MONITOR_BASE        CFG_FLASH_BASE
 #if CFG_MONITOR_BASE < CFG_FLASH_BASE
 #define CFG_RAMBOOT
 #endif
-#define        CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
+#define        CFG_MONITOR_LEN         (160 << 10)     /* Reserve 160 kB for Monitor   */
 #define        CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 
 /*
@@ -228,7 +249,7 @@
 #undef CONFIG_NVRAM_ENV
 
 #define        CFG_ENV_IS_IN_FLASH     1
-#define CFG_ENV_ADDR   (PHYS_FLASH + 0x8000)   /* Addr of Environment Sector   */
+#define CFG_ENV_ADDR   (PHYS_FLASH + 0x28000)  /* Addr of Environment Sector   */
 #define CFG_ENV_SECT_SIZE      0x8000  /* Total Size of Environment Sector     */
 
 /*-----------------------------------------------------------------------