B(supports_tv);
        B(has_bsd_ring);
        B(has_blt_ring);
+       B(has_llc);
 #undef B
 
        return 0;
 
        case I915_PARAM_HAS_GEN7_SOL_RESET:
                value = 1;
                break;
+       case I915_PARAM_HAS_LLC:
+               value = HAS_LLC(dev);
+               break;
        default:
                DRM_DEBUG_DRIVER("Unknown parameter %d\n",
                                 param->param);
 
        .need_gfx_hws = 1, .has_hotplug = 1,
        .has_bsd_ring = 1,
        .has_blt_ring = 1,
+       .has_llc = 1,
 };
 
 static const struct intel_device_info intel_sandybridge_m_info = {
        .has_fbc = 1,
        .has_bsd_ring = 1,
        .has_blt_ring = 1,
+       .has_llc = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_d_info = {
        .need_gfx_hws = 1, .has_hotplug = 1,
        .has_bsd_ring = 1,
        .has_blt_ring = 1,
+       .has_llc = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_m_info = {
        .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
        .has_bsd_ring = 1,
        .has_blt_ring = 1,
+       .has_llc = 1,
 };
 
 static const struct pci_device_id pciidlist[] = {              /* aka */
 
        u8 supports_tv:1;
        u8 has_bsd_ring:1;
        u8 has_blt_ring:1;
+       u8 has_llc:1;
 };
 
 enum no_fbc_reason {
 
 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
+#define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
 
 #define HAS_OVERLAY(dev)               (INTEL_INFO(dev)->has_overlay)
 
        obj->base.write_domain = I915_GEM_DOMAIN_CPU;
        obj->base.read_domains = I915_GEM_DOMAIN_CPU;
 
-       if (IS_GEN6(dev) || IS_GEN7(dev)) {
-               /* On Gen6, we can have the GPU use the LLC (the CPU
+       if (HAS_LLC(dev)) {
+               /* On some devices, we can have the GPU use the LLC (the CPU
                 * cache) for about a 10% performance improvement
                 * compared to uncached.  Graphics requests other than
                 * display scanout are coherent with the CPU in
 
 #define I915_PARAM_HAS_EXEC_CONSTANTS   14
 #define I915_PARAM_HAS_RELAXED_DELTA    15
 #define I915_PARAM_HAS_GEN7_SOL_RESET   16
+#define I915_PARAM_HAS_LLC              17
 
 typedef struct drm_i915_getparam {
        int param;