KVM: arm64: PMU: Move the ID_AA64DFR0_EL1.PMUver limit to VM creation

As further patches will enable the selection of a PMU revision
from userspace, sample the supported PMU revision at VM creation
time, rather than building each time the ID_AA64DFR0_EL1 register
is accessed.

This shouldn't result in any change in behaviour.

Reviewed-by: Reiji Watanabe <reijiw@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221113163832.3154370-11-maz@kernel.org

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 45e2136322ba264eb53ba1f3538df5d2c11bdb83..cc44e3bc528d88a0f4ef726118394e4be9945a01 100644 (file)
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -163,6 +163,10 @@ struct kvm_arch {
 
        u8 pfr0_csv2;
        u8 pfr0_csv3;
+       struct {
+               u8 imp:4;
+               u8 unimp:4;
+       } dfr0_pmuver;
 
        /* Hypercall features firmware registers' descriptor */
        struct kvm_smccc_features smccc_feat;

diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 94d33e296e10c57c34008af96d7a9adcb72d99ef..f956aab438c7ae96f449b12912fb52294f4acf4f 100644 (file)
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -164,6 +164,12 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
        set_default_spectre(kvm);
        kvm_arm_init_hypercalls(kvm);
 
+       /*
+        * Initialise the default PMUver before there is a chance to
+        * create an actual PMU.
+        */
+       kvm->arch.dfr0_pmuver.imp = kvm_arm_pmu_get_pmuver_limit();
+
        return ret;
 out_free_stage2_pgd:
        kvm_free_stage2_pgd(&kvm->arch.mmu);

diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index 7a945fa6dd0339ff9f903be29010db0b6f50fe1c..94ca2d17a4e46d2e984fc99b6a8d31b9070267a7 100644 (file)
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -1047,3 +1047,14 @@ int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
 
        return -ENXIO;
 }
+
+u8 kvm_arm_pmu_get_pmuver_limit(void)
+{
+       u64 tmp;
+
+       tmp = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
+       tmp = cpuid_feature_cap_perfmon_field(tmp,
+                                             ID_AA64DFR0_EL1_PMUVer_SHIFT,
+                                             ID_AA64DFR0_EL1_PMUVer_V3P4);
+       return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), tmp);
+}

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f4a7c5abcbca44070292e9a60db6f302acac783d..297b4fcbf9696f18a7e13cd33a7f0ced17ecd6e5 100644 (file)
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1062,6 +1062,27 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu,
        return true;
 }
 
+static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
+{
+       if (kvm_vcpu_has_pmu(vcpu))
+               return vcpu->kvm->arch.dfr0_pmuver.imp;
+
+       return vcpu->kvm->arch.dfr0_pmuver.unimp;
+}
+
+static u8 pmuver_to_perfmon(u8 pmuver)
+{
+       switch (pmuver) {
+       case ID_AA64DFR0_EL1_PMUVer_IMP:
+               return ID_DFR0_PERFMON_8_0;
+       case ID_AA64DFR0_EL1_PMUVer_IMP_DEF:
+               return ID_DFR0_PERFMON_IMP_DEF;
+       default:
+               /* Anything ARMv8.1+ and NI have the same value. For now. */
+               return pmuver;
+       }
+}
+
 /* Read a sanitised cpufeature ID register by sys_reg_desc */
 static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r)
 {
@@ -1111,18 +1132,17 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r
                /* Limit debug to ARMv8.0 */
                val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer);
                val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6);
-               /* Limit guests to PMUv3 for ARMv8.4 */
-               val = cpuid_feature_cap_perfmon_field(val,
-                                                     ID_AA64DFR0_EL1_PMUVer_SHIFT,
-                                                     kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_EL1_PMUVer_V3P4 : 0);
+               /* Set PMUver to the required version */
+               val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
+               val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer),
+                                 vcpu_pmuver(vcpu));
                /* Hide SPE from guests */
                val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer);
                break;
        case SYS_ID_DFR0_EL1:
-               /* Limit guests to PMUv3 for ARMv8.4 */
-               val = cpuid_feature_cap_perfmon_field(val,
-                                                     ID_DFR0_PERFMON_SHIFT,
-                                                     kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
+               val &= ~ARM64_FEATURE_MASK(ID_DFR0_PERFMON);
+               val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_PERFMON),
+                                 pmuver_to_perfmon(vcpu_pmuver(vcpu)));
                break;
        }
 

diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 96b192139a23a57a1cbac7fcb9f037dcb4df45ba..812f729c910874f3ab36d28f957c763e5f1f47c0 100644 (file)
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -89,6 +89,8 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
                        vcpu->arch.pmu.events = *kvm_get_pmu_events();  \
        } while (0)
 
+u8 kvm_arm_pmu_get_pmuver_limit(void);
+
 #else
 struct kvm_pmu {
 };
@@ -154,6 +156,10 @@ static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
 static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {}
 static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}
 static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}
+static inline u8 kvm_arm_pmu_get_pmuver_limit(void)
+{
+       return 0;
+}
 
 #endif