#define IXGBE_FUSES0_GROUP(_i)         (0x11158 + ((_i) * 4))
 #define IXGBE_FUSES0_300MHZ            BIT(5)
-#define IXGBE_FUSES0_REV1              BIT(6)
+#define IXGBE_FUSES0_REV_MASK          (3 << 6)
 
 #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
 #define IXGBE_KRM_LINK_CTRL_1(P)       ((P) ? 0x820C : 0x420C)
 
        u32 save_autoneg;
        bool link_up;
 
-       /* SW LPLU not required on later HW revisions. */
-       if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
-               return 0;
-
        /* If blocked by MNG FW, then don't restart AN */
        if (ixgbe_check_reset_blocked(hw))
                return 0;
                                              ixgbe_setup_internal_phy_t_x550em;
 
                /* setup SW LPLU only for first revision */
-               if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
-                                                       IXGBE_FUSES0_GROUP(0))))
+               if (hw->mac.type == ixgbe_mac_X550EM_x &&
+                   !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
+                     IXGBE_FUSES0_REV_MASK))
                        phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
 
                phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;