arm64: dts: imx8dxl-ss-adma: update audio node power domains and IRQ number

The power domains of i.MX8DXL's acm is difference i.MX8QXP. IRQ number of
sai[0..3] and spdif0 are also difference.

Update power domains information for i.MX8DXL.

Update sai[0..3] and spdif0's IRQ number for i.MX8DXL.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
index f5dcdd94059283710bd739187578c86be4db1385..72434529f78e693fe325ad487ba8f4d7819b37ec 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -17,6 +17,49 @@
 /delete-node/ &sai5;
 /delete-node/ &sai5_lpcg;
 
+&acm {
+       compatible = "fsl,imx8dxl-acm";
+       power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
+                       <&pd IMX_SC_R_AUDIO_CLK_1>,
+                       <&pd IMX_SC_R_MCLK_OUT_0>,
+                       <&pd IMX_SC_R_MCLK_OUT_1>,
+                       <&pd IMX_SC_R_AUDIO_PLL_0>,
+                       <&pd IMX_SC_R_AUDIO_PLL_1>,
+                       <&pd IMX_SC_R_ASRC_0>,
+                       <&pd IMX_SC_R_SAI_0>,
+                       <&pd IMX_SC_R_SAI_1>,
+                       <&pd IMX_SC_R_SAI_2>,
+                       <&pd IMX_SC_R_SAI_3>,
+                       <&pd IMX_SC_R_SPDIF_0>,
+                       <&pd IMX_SC_R_MQS_0>;
+       clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
+                <&aud_rec1_lpcg IMX_LPCG_CLK_0>,
+                <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
+                <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
+                <&clk_ext_aud_mclk0>,
+                <&clk_ext_aud_mclk1>,
+                <&clk_spdif0_rx>,
+                <&clk_sai0_rx_bclk>,
+                <&clk_sai0_tx_bclk>,
+                <&clk_sai1_rx_bclk>,
+                <&clk_sai1_tx_bclk>,
+                <&clk_sai2_rx_bclk>,
+                <&clk_sai3_rx_bclk>;
+       clock-names = "aud_rec_clk0_lpcg_clk",
+                     "aud_rec_clk1_lpcg_clk",
+                     "aud_pll_div_clk0_lpcg_clk",
+                     "aud_pll_div_clk1_lpcg_clk",
+                     "ext_aud_mclk0",
+                     "ext_aud_mclk1",
+                     "spdif0_rx",
+                     "sai0_rx_bclk",
+                     "sai0_tx_bclk",
+                     "sai1_rx_bclk",
+                     "sai1_tx_bclk",
+                     "sai2_rx_bclk",
+                     "sai3_rx_bclk";
+};
+
 &audio_ipg_clk {
        clock-frequency = <160000000>;
 };
@@ -191,3 +234,24 @@
 &lpspi3 {
        interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 };
+
+&sai0 {
+       interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sai1 {
+       interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sai2 {
+       interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sai3 {
+       interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spdif0 {
+       interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+                    <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+};