drm/i915/dg2: Tile 4 plane format support

TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.

v2: - Fixed wrong case condition(Jani Nikula)
    - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)

v3: - s/I915_TILING_F/TILING_4/g
    - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
    - Removed unneeded fencing code

v4: - Rebased, fixed merge conflict with new table-oriented
      format modifier checking(Stan)
    - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)

v5: - Still had to remove some Tile F mentionings
    - Moved has_4tile from adlp to DG2(Ramalingam C)
    - Check specifically for DG2, but not the Display13(Imre)

v6: - Moved Tile4 associating struct for modifier/display to
      the beginning(Imre Deak)
    - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
      checks(Imre Deak)
    - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
      (Imre Deak)

v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
    - Removed redundant newline(Imre Deak)

Reviewed-by: Imre Deak <imre.deak@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211122211420.31584-1-stanislav.lisovskiy@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f3c9208a30b1677d435107d231270a0b253b1116..7429965d368287cf7c46abac51e0356af185f1a3 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
                case I915_FORMAT_MOD_X_TILED:
                case I915_FORMAT_MOD_Y_TILED:
                case I915_FORMAT_MOD_Yf_TILED:
+               case I915_FORMAT_MOD_4_TILED:
                        break;
                default:
                        drm_dbg_kms(&i915->drm,

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index c4a743d0913fc817b9fab7f4c1da6b4c547052ff..b7f1ef62072cea314af9e76483b56faf2ac2e46a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -139,6 +139,9 @@ struct intel_modifier_desc {
 
 static const struct intel_modifier_desc intel_modifiers[] = {
        {
+               .modifier = I915_FORMAT_MOD_4_TILED,
+               .display_ver = { 13, 13 },
+       }, {
                .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
                .display_ver = { 12, 13 },
                .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
@@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
                        return 128;
                else
                        return 512;
+       case I915_FORMAT_MOD_4_TILED:
+               /*
+                * Each 4K tile consists of 64B(8*8) subtiles, with
+                * same shape as Y Tile(i.e 4*16B OWords)
+                */
+               return 128;
        case I915_FORMAT_MOD_Y_TILED_CCS:
                if (intel_fb_is_ccs_aux_plane(fb, color_plane))
                        return 128;

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index d0c34bc3af6c27d5a40e7da869bd57296bcd76b4..0ceabe40d8c9dcf61ace782e767429ec72df60a8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915,
        case I915_FORMAT_MOD_Y_TILED:
        case I915_FORMAT_MOD_Yf_TILED:
                return DISPLAY_VER(i915) >= 9;
+       case I915_FORMAT_MOD_4_TILED:
        case I915_FORMAT_MOD_X_TILED:
                return true;
        default:

diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index dcd698a02da21f9953e39aa2b5ffb0ed17e49330..d80855ee9b961a714ab6004817393b5bc01aa1a9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
        case DRM_FORMAT_MOD_LINEAR:
        case I915_FORMAT_MOD_X_TILED:
        case I915_FORMAT_MOD_Y_TILED:
+       case I915_FORMAT_MOD_4_TILED:
                break;
        default:
                drm_dbg(&dev_priv->drm,

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 28890876bdebff079598e8b165f3360b45cbf752..e5cda5bcbde4121344ffcdc5a679e659c664bf52 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
                return PLANE_CTL_TILED_X;
        case I915_FORMAT_MOD_Y_TILED:
                return PLANE_CTL_TILED_Y;
+       case I915_FORMAT_MOD_4_TILED:
+               return PLANE_CTL_TILED_4;
        case I915_FORMAT_MOD_Y_TILED_CCS:
        case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
                return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
        case DRM_FORMAT_Y216:
        case DRM_FORMAT_XVYU12_16161616:
        case DRM_FORMAT_XVYU16161616:
-               if (modifier == DRM_FORMAT_MOD_LINEAR ||
-                   modifier == I915_FORMAT_MOD_X_TILED ||
-                   modifier == I915_FORMAT_MOD_Y_TILED)
+               if (!intel_fb_is_ccs_modifier(modifier))
                        return true;
                fallthrough;
        default:
@@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
                else
                        fb->modifier = I915_FORMAT_MOD_Y_TILED;
                break;
-       case PLANE_CTL_TILED_YF:
-               if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
-                       fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
-               else
-                       fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+       case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
+               if (HAS_4TILE(dev_priv)) {
+                       fb->modifier = I915_FORMAT_MOD_4_TILED;
+               } else {
+                       if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+                               fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
+                       else
+                               fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+               }
                break;
        default:
                MISSING_CASE(tiling);

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4f58e145650570f29c3bb6b85c86f8ff7f2cfaef..250ac161f55c5480171945938914d6875bb959e5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1624,6 +1624,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
 
 #define HAS_LLC(dev_priv)      (INTEL_INFO(dev_priv)->has_llc)
+#define HAS_4TILE(dev_priv)    (INTEL_INFO(dev_priv)->has_4tile)
 #define HAS_SNOOP(dev_priv)    (INTEL_INFO(dev_priv)->has_snoop)
 #define HAS_EDRAM(dev_priv)    ((dev_priv)->edram_size_mb)
 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 52749b8f4f6b80139603a4437d3b93eda7a2bd2a..69b8029da6b6128a4206d1a0163d5d184a299a2e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = {
        DGFX_FEATURES,
        .graphics_rel = 55,
        .media_rel = 55,
+       .has_4tile = 1,
        PLATFORM(INTEL_DG2),
        .platform_engine_mask =
                BIT(RCS0) | BIT(BCS0) |

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47fcd104868fe89568e650e60fba4baa8c4b4324..38b4e3b5d8b2c36f9ef89bc05f39bf8a13999ea2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7210,6 +7210,7 @@ enum {
 #define   PLANE_CTL_TILED_X                    (1 << 10)
 #define   PLANE_CTL_TILED_Y                    (4 << 10)
 #define   PLANE_CTL_TILED_YF                   (5 << 10)
+#define   PLANE_CTL_TILED_4                    (5 << 10)
 #define   PLANE_CTL_ASYNC_FLIP                 (1 << 9)
 #define   PLANE_CTL_FLIP_HORIZONTAL            (1 << 8)
 #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 8e6f48d1eb7bcb4402d4b777d5c32076fb206078..6c543a1522508254411aed2350de85d3d21040f2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,7 @@ enum intel_ppgtt_type {
        func(has_64bit_reloc); \
        func(gpu_reset_clobbers_display); \
        func(has_reset_engine); \
+       func(has_4tile); \
        func(has_global_mocs); \
        func(has_gt_uc); \
        func(has_l3_dpf); \

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e9f2e307b98e48b6d7eecd27301d6519e8b381a7..2ad577dfe5040cb4c29ae4f281c226913b92f292 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
        }
 
        wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
+                     modifier == I915_FORMAT_MOD_4_TILED ||
                      modifier == I915_FORMAT_MOD_Yf_TILED ||
                      modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
                      modifier == I915_FORMAT_MOD_Yf_TILED_CCS;

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 7f652c96845ba68d2dbc6a996e2cb453d5b13a4e..41184a94935d5a87d6fd0d803d65daa8d4d29f9c 100644 (file)
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -564,6 +564,14 @@ extern "C" {
  * pitch is required to be a multiple of 4 tile widths.
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+/*
+ * Intel F-tiling(aka Tile4) layout
+ *
+ * This is a tiled layout using 4Kb tiles in row-major layout.
+ * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
+ * (16 bytes) chunks column-major..
+ */
+#define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
 
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks