phy: ti: phy-j721e-wiz: split wiz_clock_init() function

The wiz_clock_init() function mixes probe and hardware configuration.
Rename the wiz_clock_init() to wiz_clock_probe() and move the hardware
configuration part in a new function named wiz_clock_init().

This hardware configuration sequence must be called during the resume
stage of the driver.

Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-2-f15815833974@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 5fea4df9404e08d9727d8a4fcefd09003c7c1be6..ba670109e7ad43b1e80cd2e44d9ac59419c1af8a 100644 (file)
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -1076,26 +1076,12 @@ static int wiz_clock_register(struct wiz *wiz)
        return ret;
 }
 
-static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
+static void wiz_clock_init(struct wiz *wiz)
 {
-       const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
-       struct device *dev = wiz->dev;
-       struct device_node *clk_node;
-       const char *node_name;
        unsigned long rate;
-       struct clk *clk;
-       int ret;
-       int i;
-
-       clk = devm_clk_get(dev, "core_ref_clk");
-       if (IS_ERR(clk))
-               return dev_err_probe(dev, PTR_ERR(clk),
-                                    "core_ref_clk clock not found\n");
 
-       wiz->input_clks[WIZ_CORE_REFCLK] = clk;
-
-       rate = clk_get_rate(clk);
-       if (rate >= 100000000)
+       rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK]);
+       if (rate >= REF_CLK_100MHZ)
                regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
        else
                regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
@@ -1119,6 +1105,38 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
                break;
        }
 
+       if (wiz->input_clks[WIZ_CORE_REFCLK1]) {
+               rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK1]);
+               if (rate >= REF_CLK_100MHZ)
+                       regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
+               else
+                       regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
+       }
+
+       rate = clk_get_rate(wiz->input_clks[WIZ_EXT_REFCLK]);
+       if (rate >= REF_CLK_100MHZ)
+               regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
+       else
+               regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
+}
+
+static int wiz_clock_probe(struct wiz *wiz, struct device_node *node)
+{
+       const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
+       struct device *dev = wiz->dev;
+       struct device_node *clk_node;
+       const char *node_name;
+       struct clk *clk;
+       int ret;
+       int i;
+
+       clk = devm_clk_get(dev, "core_ref_clk");
+       if (IS_ERR(clk))
+               return dev_err_probe(dev, PTR_ERR(clk),
+                                    "core_ref_clk clock not found\n");
+
+       wiz->input_clks[WIZ_CORE_REFCLK] = clk;
+
        if (wiz->data->pma_cmn_refclk1_int_mode) {
                clk = devm_clk_get(dev, "core_ref1_clk");
                if (IS_ERR(clk))
@@ -1126,12 +1144,6 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
                                             "core_ref1_clk clock not found\n");
 
                wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
-
-               rate = clk_get_rate(clk);
-               if (rate >= 100000000)
-                       regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
-               else
-                       regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
        }
 
        clk = devm_clk_get(dev, "ext_ref_clk");
@@ -1141,11 +1153,7 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
 
        wiz->input_clks[WIZ_EXT_REFCLK] = clk;
 
-       rate = clk_get_rate(clk);
-       if (rate >= 100000000)
-               regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
-       else
-               regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
+       wiz_clock_init(wiz);
 
        switch (wiz->type) {
        case AM64_WIZ_10G:
@@ -1589,7 +1597,7 @@ static int wiz_probe(struct platform_device *pdev)
                goto err_get_sync;
        }
 
-       ret = wiz_clock_init(wiz, node);
+       ret = wiz_clock_probe(wiz, node);
        if (ret < 0) {
                dev_warn(dev, "Failed to initialize clocks\n");
                goto err_get_sync;