drm/i915: pass dev_priv explicitly to PIPE_LINK_M1

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_LINK_M1 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/bf25d447d98009f56f2c5b2205719ab2d9a70c93.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7bf5b255914349be8d8a69a5e683085d19c5d3ca..a3249d782a8b4538ccb64c571d245928bc6afc46 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2643,7 +2643,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
                intel_set_m_n(dev_priv, m_n,
                              PIPE_DATA_M1(dev_priv, transcoder),
                              PIPE_DATA_N1(dev_priv, transcoder),
-                             PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
+                             PIPE_LINK_M1(dev_priv, transcoder),
+                             PIPE_LINK_N1(transcoder));
        else
                intel_set_m_n(dev_priv, m_n,
                              PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
@@ -3341,7 +3342,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
                intel_get_m_n(dev_priv, m_n,
                              PIPE_DATA_M1(dev_priv, transcoder),
                              PIPE_DATA_N1(dev_priv, transcoder),
-                             PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
+                             PIPE_LINK_M1(dev_priv, transcoder),
+                             PIPE_LINK_N1(transcoder));
        else
                intel_get_m_n(dev_priv, m_n,
                              PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),

diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 5f3ee57b59823723b196985005b108a0242d0900..eea956603cc81d67f55f8cae2e278a30fa270d21 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -264,7 +264,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
                vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
                vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
                vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
-               vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
+               vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
                vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
 
                /* Enable per-DDI/PORT vreg */
@@ -398,7 +398,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
                vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
                vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
                vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
-               vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
+               vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
                vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
        }
 

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index bffbefe5fd31ed5824bca9a8a5ddf9cb241323ac..d0c4e555435a76c9a4f3b60f84f65f32270ccc92 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -672,7 +672,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
                dp_br = skl_vgpu_get_dp_bitrate(vgpu, port);
 
        /* Get DP link symbol clock M/N */
-       link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A));
+       link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A));
        link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A));
 
        /* Get H/V total from transcoder timing */

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87c06eadf248e12b9fed864a8740a930d89d2875..f45bb6d5705bc759290e359f7f567e8c53b5dc5d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2302,7 +2302,7 @@
 #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
 #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
 #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
-#define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
+#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 829196c665c6e52239684e2148de21c02c0584af..c08b8e75537762dc799d936fe89d27106456181d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -270,7 +270,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
        MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
        MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));
-       MMIO_D(PIPE_LINK_M1(TRANSCODER_A));
+       MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
        MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
        MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
        MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
@@ -278,7 +278,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
        MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
        MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));
-       MMIO_D(PIPE_LINK_M1(TRANSCODER_B));
+       MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
        MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
        MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
        MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
@@ -286,7 +286,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
        MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
        MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));
-       MMIO_D(PIPE_LINK_M1(TRANSCODER_C));
+       MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
        MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
        MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
        MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
@@ -294,7 +294,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
        MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
        MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));
-       MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP));
+       MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
        MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP));
        MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP));
        MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP));