u32 dvma_addr = (u32)dbri->dma_dvma;
s32 *cmd;
u32 dma_addr;
- unsigned long flags;
int n;
- spin_lock_irqsave(&dbri->lock, flags);
-
- dbri_reset(dbri);
+ scoped_guard(spinlock_irqsave, &dbri->lock) {
+ dbri_reset(dbri);
- /* Initialize pipes */
- for (n = 0; n < DBRI_NO_PIPES; n++)
- dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
+ /* Initialize pipes */
+ for (n = 0; n < DBRI_NO_PIPES; n++)
+ dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
- spin_lock_init(&dbri->cmdlock);
- /*
- * Initialize the interrupt ring buffer.
- */
- dma_addr = dvma_addr + dbri_dma_off(intr, 0);
- dbri->dma->intr[0] = dma_addr;
- dbri->dbri_irqp = 1;
- /*
- * Set up the interrupt queue
- */
- spin_lock(&dbri->cmdlock);
- cmd = dbri->cmdptr = dbri->dma->cmd;
- *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
- *(cmd++) = dma_addr;
- *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
- dbri->cmdptr = cmd;
- *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
- *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
- dma_addr = dvma_addr + dbri_dma_off(cmd, 0);
- sbus_writel(dma_addr, dbri->regs + REG8);
- spin_unlock(&dbri->cmdlock);
+ spin_lock_init(&dbri->cmdlock);
+ /*
+ * Initialize the interrupt ring buffer.
+ */
+ dma_addr = dvma_addr + dbri_dma_off(intr, 0);
+ dbri->dma->intr[0] = dma_addr;
+ dbri->dbri_irqp = 1;
+ /*
+ * Set up the interrupt queue
+ */
+ scoped_guard(spinlock, &dbri->cmdlock) {
+ cmd = dbri->cmdptr = dbri->dma->cmd;
+ *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
+ *(cmd++) = dma_addr;
+ *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
+ dbri->cmdptr = cmd;
+ *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
+ *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
+ dma_addr = dvma_addr + dbri_dma_off(cmd, 0);
+ sbus_writel(dma_addr, dbri->regs + REG8);
+ }
+ }
- spin_unlock_irqrestore(&dbri->lock, flags);
dbri_cmdwait(dbri);
}
static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
{
s32 *cmd;
- unsigned long flags;
if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
*(cmd++) = data;
*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
- spin_lock_irqsave(&dbri->lock, flags);
- dbri_cmdsend(dbri, cmd, 3);
- spin_unlock_irqrestore(&dbri->lock, flags);
+ scoped_guard(spinlock_irqsave, &dbri->lock) {
+ dbri_cmdsend(dbri, cmd, 3);
+ }
+
dbri_cmdwait(dbri);
}
*/
static void cs4215_setup_pipes(struct snd_dbri *dbri)
{
- unsigned long flags;
-
- spin_lock_irqsave(&dbri->lock, flags);
- /*
- * Data mode:
- * Pipe 4: Send timeslots 1-4 (audio data)
- * Pipe 20: Send timeslots 5-8 (part of ctrl data)
- * Pipe 6: Receive timeslots 1-4 (audio data)
- * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
- * interrupt, and the rest of the data (slot 5 and 8) is
- * not relevant for us (only for doublechecking).
- *
- * Control mode:
- * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
- * Pipe 18: Receive timeslot 1 (clb).
- * Pipe 19: Receive timeslot 7 (version).
- */
+ scoped_guard(spinlock_irqsave, &dbri->lock) {
+ /*
+ * Data mode:
+ * Pipe 4: Send timeslots 1-4 (audio data)
+ * Pipe 20: Send timeslots 5-8 (part of ctrl data)
+ * Pipe 6: Receive timeslots 1-4 (audio data)
+ * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
+ * interrupt, and the rest of the data (slot 5 and 8) is
+ * not relevant for us (only for doublechecking).
+ *
+ * Control mode:
+ * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
+ * Pipe 18: Receive timeslot 1 (clb).
+ * Pipe 19: Receive timeslot 7 (version).
+ */
- setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
- setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
- setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
- setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
+ setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
+ setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
+ setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
+ setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
- setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
- setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
- setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
- spin_unlock_irqrestore(&dbri->lock, flags);
+ setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
+ setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
+ setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
+ }
dbri_cmdwait(dbri);
}
{
int data_width;
u32 tmp;
- unsigned long flags;
dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
dbri->mm.channels, dbri->mm.precision);
* bits. The CS4215, it seems, observes TSIN (the delayed signal)
* even if it's the CHI master. Don't ask me...
*/
- spin_lock_irqsave(&dbri->lock, flags);
- tmp = sbus_readl(dbri->regs + REG0);
- tmp &= ~(D_C); /* Disable CHI */
- sbus_writel(tmp, dbri->regs + REG0);
+ scoped_guard(spinlock_irqsave, &dbri->lock) {
+ tmp = sbus_readl(dbri->regs + REG0);
+ tmp &= ~(D_C); /* Disable CHI */
+ sbus_writel(tmp, dbri->regs + REG0);
- /* Switch CS4215 to data mode - set PIO3 to 1 */
- sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
- (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
+ /* Switch CS4215 to data mode - set PIO3 to 1 */
+ sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
+ (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
- reset_chi(dbri, CHIslave, 128);
+ reset_chi(dbri, CHIslave, 128);
- /* Note: this next doesn't work for 8-bit stereo, because the two
- * channels would be on timeslots 1 and 3, with 2 and 4 idle.
- * (See CS4215 datasheet Fig 15)
- *
- * DBRI non-contiguous mode would be required to make this work.
- */
- data_width = dbri->mm.channels * dbri->mm.precision;
+ /* Note: this next doesn't work for 8-bit stereo, because the two
+ * channels would be on timeslots 1 and 3, with 2 and 4 idle.
+ * (See CS4215 datasheet Fig 15)
+ *
+ * DBRI non-contiguous mode would be required to make this work.
+ */
+ data_width = dbri->mm.channels * dbri->mm.precision;
- link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
- link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
- link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
- link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
+ link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
+ link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
+ link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
+ link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
- /* FIXME: enable CHI after _setdata? */
- tmp = sbus_readl(dbri->regs + REG0);
- tmp |= D_C; /* Enable CHI */
- sbus_writel(tmp, dbri->regs + REG0);
- spin_unlock_irqrestore(&dbri->lock, flags);
+ /* FIXME: enable CHI after _setdata? */
+ tmp = sbus_readl(dbri->regs + REG0);
+ tmp |= D_C; /* Enable CHI */
+ sbus_writel(tmp, dbri->regs + REG0);
+ }
cs4215_setdata(dbri, 0);
}
{
int i, val;
u32 tmp;
- unsigned long flags;
/* FIXME - let the CPU do something useful during these delays */
* done in hardware by a TI 248 that delays the DBRI->4215
* frame sync signal by eight clock cycles. Anybody know why?
*/
- spin_lock_irqsave(&dbri->lock, flags);
- tmp = sbus_readl(dbri->regs + REG0);
- tmp &= ~D_C; /* Disable CHI */
- sbus_writel(tmp, dbri->regs + REG0);
-
- reset_chi(dbri, CHImaster, 128);
-
- /*
- * Control mode:
- * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
- * Pipe 18: Receive timeslot 1 (clb).
- * Pipe 19: Receive timeslot 7 (version).
- */
+ scoped_guard(spinlock_irqsave, &dbri->lock) {
+ tmp = sbus_readl(dbri->regs + REG0);
+ tmp &= ~D_C; /* Disable CHI */
+ sbus_writel(tmp, dbri->regs + REG0);
+
+ reset_chi(dbri, CHImaster, 128);
+
+ /*
+ * Control mode:
+ * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
+ * Pipe 18: Receive timeslot 1 (clb).
+ * Pipe 19: Receive timeslot 7 (version).
+ */
- link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
- link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
- link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
- spin_unlock_irqrestore(&dbri->lock, flags);
+ link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
+ link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
+ link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
+ }
/* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
dbri->mm.ctrl[0] &= ~CS4215_CLB;
xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
- spin_lock_irqsave(&dbri->lock, flags);
- tmp = sbus_readl(dbri->regs + REG0);
- tmp |= D_C; /* Enable CHI */
- sbus_writel(tmp, dbri->regs + REG0);
- spin_unlock_irqrestore(&dbri->lock, flags);
+ scoped_guard(spinlock_irqsave, &dbri->lock) {
+ tmp = sbus_readl(dbri->regs + REG0);
+ tmp |= D_C; /* Enable CHI */
+ sbus_writel(tmp, dbri->regs + REG0);
+ }
for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
msleep_interruptible(1);
struct dbri_streaminfo *info;
u32 dvma_addr;
s32 *cmd;
- unsigned long flags;
int first_td;
if (dbri == NULL)
dvma_addr = (u32)dbri->dma_dvma;
info = &dbri->stream_info[DBRI_REC];
- spin_lock_irqsave(&dbri->lock, flags);
+ guard(spinlock_irqsave)(&dbri->lock);
if (info->pipe >= 0) {
first_td = dbri->pipes[info->pipe].first_desc;
dbri->pipes[info->pipe].desc = first_td;
}
}
-
- spin_unlock_irqrestore(&dbri->lock, flags);
}
/* transmission_complete_intr()
if (dbri == NULL)
return IRQ_NONE;
- spin_lock(&dbri->lock);
+ guard(spinlock)(&dbri->lock);
/*
* Read it, so the interrupt goes away.
dbri_process_interrupt_buffer(dbri);
- spin_unlock(&dbri->lock);
-
return IRQ_HANDLED;
}
struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
- unsigned long flags;
dprintk(D_USR, "open audio output.\n");
runtime->hw = snd_dbri_pcm_hw;
- spin_lock_irqsave(&dbri->lock, flags);
- info->substream = substream;
- info->offset = 0;
- info->dvma_buffer = 0;
- info->pipe = -1;
- spin_unlock_irqrestore(&dbri->lock, flags);
+ scoped_guard(spinlock_irqsave, &dbri->lock) {
+ info->substream = substream;
+ info->offset = 0;
+ info->dvma_buffer = 0;
+ info->pipe = -1;
+ }
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
else
info->pipe = 6; /* Receive pipe */
- spin_lock_irq(&dbri->lock);
+ guard(spinlock_irq)(&dbri->lock);
info->offset = 0;
/* Setup the all the transmit/receive descriptors to cover the
ret = setup_descs(dbri, DBRI_STREAMNO(substream),
snd_pcm_lib_period_bytes(substream));
- spin_unlock_irq(&dbri->lock);
-
dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
return ret;
}
projects / users / hch / misc.git / commitdiff