atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 
-       if (ASIC_IS_DCE8(rdev)) {
+       if (ASIC_IS_DCE8(rdev))
                WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
-       }
 }
 
 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
 
        dp_info.use_dpencoder = true;
        index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
        if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
-               if (crev > 1) {
+               if (crev > 1)
                        dp_info.use_dpencoder = false;
-               }
        }
 
        dp_info.enc_id = 0;
 
                        if (ASIC_IS_AVIVO(rdev))
                                args.v1.ucCRTC = radeon_crtc->crtc_id;
                        else {
-                               if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
+                               if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)
                                        args.v1.ucCRTC = radeon_crtc->crtc_id;
-                               } else {
+                               else
                                        args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
-                               }
                        }
                        switch (radeon_encoder->encoder_id) {
                        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
                DRM_ERROR("Got encoder index incorrect - returning 0\n");
                return 0;
        }
-       if (rdev->mode_info.active_encoders & (1 << enc_idx)) {
+       if (rdev->mode_info.active_encoders & (1 << enc_idx))
                DRM_ERROR("chosen encoder in use %d\n", enc_idx);
-       }
+
        rdev->mode_info.active_encoders |= (1 << enc_idx);
        return enc_idx;
 }
 
                        else
                                ret = radeon_legacy_get_tmds_info_from_combios(radeon_encoder, tmds);
                }
-               if (val == 1 || !ret) {
+               if (val == 1 || !ret)
                        radeon_legacy_get_tmds_info_from_table(radeon_encoder, tmds);
-               }
+
                radeon_property_change_mode(&radeon_encoder->base);
        }
 
 
                ib.ptr[i] = cpu_to_le32(0x0);
 
        r = radeon_ib_schedule(rdev, &ib, NULL, false);
-       if (r) {
+       if (r)
                DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
-       }
+
 
        if (fence)
                *fence = radeon_fence_ref(ib.fence);
 
        struct radeon_bo_va *bo_va;
 
        list_for_each_entry(bo_va, &bo->va, bo_list) {
-               if (bo_va->vm == vm) {
+               if (bo_va->vm == vm)
                        return bo_va;
-               }
+
        }
        return NULL;
 }
        struct radeon_bo_va *bo_va;
 
        bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
-       if (bo_va == NULL) {
+       if (bo_va == NULL)
                return NULL;
-       }
+
        bo_va->vm = vm;
        bo_va->bo = bo;
        bo_va->it.start = 0;
 
        if (mem) {
                addr = (u64)mem->start << PAGE_SHIFT;
-               if (mem->mem_type != TTM_PL_SYSTEM) {
+               if (mem->mem_type != TTM_PL_SYSTEM)
                        bo_va->flags |= RADEON_VM_PAGE_VALID;
-               }
+
                if (mem->mem_type == TTM_PL_TT) {
                        bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
                        if (!(bo_va->bo->flags & (RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC)))
        struct radeon_bo_va *bo_va, *tmp;
        int i, r;
 
-       if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
+       if (!RB_EMPTY_ROOT(&vm->va.rb_root))
                dev_err(rdev->dev, "still active bo inside vm\n");
-       }
+
        rbtree_postorder_for_each_entry_safe(bo_va, tmp,
                                             &vm->va.rb_root, it.rb) {
                interval_tree_remove(&bo_va->it, &vm->va);