# Note that GCC does not numerically define an architecture version
  # macro, but instead defines a whole series of macros which makes
  # testing for a specific architecture or later rather impossible.
 -arch-$(CONFIG_CPU_32v7M)      :=-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
 -arch-$(CONFIG_CPU_32v7)               :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
 -arch-$(CONFIG_CPU_32v6)               :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
++arch-$(CONFIG_CPU_32v7M)      =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
 +arch-$(CONFIG_CPU_32v7)               =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
 +arch-$(CONFIG_CPU_32v6)               =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
  # Only override the compiler option if ARMv6. The ARMv6K extensions are
  # always available in ARMv7
  ifeq ($(CONFIG_CPU_32v6),y)
 
  # endif
  #endif
  
+ #ifdef CONFIG_CPU_V7M
+ # ifdef CPU_NAME
+ #  undef  MULTI_CPU
+ #  define MULTI_CPU
+ # else
+ #  define CPU_NAME cpu_v7m
+ # endif
+ #endif
+ 
 +#ifdef CONFIG_CPU_PJ4B
 +# ifdef CPU_NAME
 +#  undef  MULTI_CPU
 +#  define MULTI_CPU
 +# else
 +#  define CPU_NAME cpu_pj4b
 +# endif
 +#endif
 +
  #ifndef MULTI_CPU
  #define cpu_proc_init                 __glue(CPU_NAME,_proc_init)
  #define cpu_proc_fin                  __glue(CPU_NAME,_proc_fin)
 
        str     lr, [sp, #S_PC]                 @ Save calling PC
        str     r8, [sp, #S_PSR]                @ Save CPSR
        str     r0, [sp, #S_OLD_R0]             @ Save OLD_R0
+ #endif
        zero_fp
  
 +#ifdef CONFIG_ALIGNMENT_TRAP
 +      ldr     ip, __cr_alignment
 +      ldr     ip, [ip]
 +      mcr     p15, 0, ip, c1, c0              @ update control register
 +#endif
 +
 +      enable_irq
 +      ct_user_exit
 +      get_thread_info tsk
 +
        /*
         * Get the system call number.
         */
 
              "I" (offsetof(struct stack, und[0])),
              PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
            : "r14");
+ #endif
  }
  
 -int __cpu_logical_map[NR_CPUS];
 +u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
  
  void __init smp_setup_processor_id(void)
  {
 
        /*
         * Marvell PJ4B processor.
         */
 +#ifdef CONFIG_CPU_PJ4B
        .type   __v7_pj4b_proc_info, #object
  __v7_pj4b_proc_info:
 -      .long   0x562f5840
 -      .long   0xfffffff0
 -      __v7_proc __v7_pj4b_setup
 +      .long   0x560f5800
 +      .long   0xff0fff00
 +      __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
        .size   __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 +#endif
  
+       /*
+        * ARM Ltd. Cortex R7 processor.
+        */
+       .type   __v7_cr7mp_proc_info, #object
+ __v7_cr7mp_proc_info:
+       .long   0x410fc170
+       .long   0xff0ffff0
+       __v7_proc __v7_cr7mp_setup
+       .size   __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
+ 
        /*
         * ARM Ltd. Cortex A7 processor.
         */