MIPS: cevt-r4k: Use CAUSEF_TI, CAUSEF_PCI constants

Use CAUSEF_TI and CAUSEF_PCI constants from asm/mipsregs.h rather than
the magic values (1 << 30) and (1 << 26).

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9124/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 623f0bcfcaf10425de31650bb67adf1df3e54ba6..43ae718707970fa387e279d42fabffc16c75c71a 100644 (file)
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -75,7 +75,7 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
         * above we now know that the reason we got here must be a timer
         * interrupt.  Being the paranoiacs we are we check anyway.
         */
-       if (!r2 || (read_c0_cause() & (1 << 30))) {
+       if (!r2 || (read_c0_cause() & CAUSEF_TI)) {
                /* Clear Count/Compare Interrupt */
                write_c0_compare(read_c0_compare());
                cd = &per_cpu(mips_clockevent_device, cpu);

diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 01f721a85c5b390a42553403c27875a4ee4e8cec..faf0d4ad0cc2adebccf3d278d7bd1f1b3394cb18 100644 (file)
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -246,7 +246,7 @@ static int mipsxx_perfcount_handler(void)
        unsigned int counter;
        int handled = IRQ_NONE;
 
-       if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
+       if (cpu_has_mips_r2 && !(read_c0_cause() & CAUSEF_PCI))
                return handled;
 
        switch (counters) {