Move pp_feature from the struct of amd_powerplay to amdgpu_device.
Add pp_feature limit for overdrive interface.
v2: put pp_feature into struct amdgpu_pm.
v3: merge feature_mask with pp_feature.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Suggested-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 struct amd_powerplay {
        void *pp_handle;
        const struct amd_pm_funcs *pp_funcs;
-       uint32_t pp_feature;
 };
 
 #define AMDGPU_RESET_MAGIC_NUM 64
 
                        return -EAGAIN;
        }
 
-       adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
+       adev->pm.pp_feature = amdgpu_pp_feature_mask;
 
        for (i = 0; i < adev->num_ip_blocks; i++) {
                if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
 
        uint32_t                smu_prv_buffer_size;
        struct amdgpu_bo        *smu_prv_buffer;
        bool ac_power;
+       /* powerplay feature */
+       uint32_t pp_feature;
+
 };
 
 #define R600_SSTU_DFLT                               0
 
 
 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 {
-       if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK))
+       if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
                return;
 
        if (!adev->powerplay.pp_funcs || !adev->powerplay.pp_funcs->set_powergating_by_smu)
 
                                "pp_power_profile_mode\n");
                return ret;
        }
-       if (is_support_sw_smu(adev) || hwmgr->od_enabled) {
+       if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
+           (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
                ret = device_create_file(adev->dev,
                                &dev_attr_pp_od_clk_voltage);
                if (ret) {
        device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
        device_remove_file(adev->dev,
                        &dev_attr_pp_power_profile_mode);
-       if (hwmgr->od_enabled)
+       if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
+           (!is_support_sw_smu(adev) && hwmgr->od_enabled))
                device_remove_file(adev->dev,
                                &dev_attr_pp_od_clk_voltage);
        device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
 
                pi->caps_tcp_ramping = true;
        }
 
-       if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
+       if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
                pi->caps_sclk_ds = true;
        else
                pi->caps_sclk_ds = false;
 
                        adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
                }
 
-               if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
+               if (adev->pm.pp_feature & PP_GFXOFF_MASK)
                        adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
                                AMD_PG_SUPPORT_CP |
                                AMD_PG_SUPPORT_RLC_SMU_HS;
 
        mutex_init(&hwmgr->smu_lock);
        hwmgr->chip_family = adev->family;
        hwmgr->chip_id = adev->asic_type;
-       hwmgr->feature_mask = adev->powerplay.pp_feature;
+       hwmgr->feature_mask = adev->pm.pp_feature;
        hwmgr->display_config = &adev->pm.pm_display_cfg;
        adev->powerplay.pp_handle = hwmgr;
        adev->powerplay.pp_funcs = &pp_dpm_funcs;
 
 
        switch (adev->asic_type) {
        case CHIP_VEGA20:
+               adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+               if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+                       smu->od_enabled = true;
                smu_v11_0_set_smu_funcs(smu);
                break;
        default:
 
        uint32_t pstate_sclk;
        uint32_t pstate_mclk;
 
+       bool od_enabled;
        uint32_t power_limit;
        uint32_t default_power_limit;