wifi: rtw89: phy: set TX power offset according to chip gen

We have a register to control TX power of each rate section to increase
or decrease an offset. But, Wi-Fi 6 chips and Wi-Fi 7 chips have different
address and format for this control register. We rename original setting
stuffs with a suffix `_ax` and implement setting flow for Wi-Fi 7 chips.
Then, we set TX power offset according to chip generation.

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231003015446.14658-4-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c
index 02056936dc7c140af59f467925d92df31f1be1be..c7dad5bf50f7ed9120dc16531e845535aaaa359f 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/phy.c
+++ b/drivers/net/wireless/realtek/rtw89/phy.c
@@ -2153,9 +2153,10 @@ static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev,
        }
 }
 
-void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
-                               const struct rtw89_chan *chan,
-                               enum rtw89_phy_idx phy_idx)
+static
+void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev,
+                                  const struct rtw89_chan *chan,
+                                  enum rtw89_phy_idx phy_idx)
 {
        struct rtw89_rate_desc desc = {
                .nss = RTW89_NSS_1,
@@ -2180,7 +2181,6 @@ void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
        rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
                                     GENMASK(19, 0), val);
 }
-EXPORT_SYMBOL(rtw89_phy_set_txpwr_offset);
 
 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
                               const struct rtw89_chan *chan,
@@ -4905,5 +4905,6 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
        .physts = &rtw89_physts_regs_ax,
 
        .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax,
+       .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax,
 };
 EXPORT_SYMBOL(rtw89_phy_gen_ax);

diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h
index 78beafda3726626bd0a0e78c852e6cd1b4325b44..d69054c52df170926ce490246d08feed553bf775 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/phy.h
+++ b/drivers/net/wireless/realtek/rtw89/phy.h
@@ -408,6 +408,9 @@ struct rtw89_phy_gen_def {
        void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev,
                                 const struct rtw89_chan *chan,
                                 enum rtw89_phy_idx phy_idx);
+       void (*set_txpwr_offset)(struct rtw89_dev *rtwdev,
+                                const struct rtw89_chan *chan,
+                                enum rtw89_phy_idx phy_idx);
 };
 
 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax;
@@ -637,9 +640,16 @@ void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
        phy->set_txpwr_byrate(rtwdev, chan, phy_idx);
 }
 
+static inline
 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
                                const struct rtw89_chan *chan,
-                               enum rtw89_phy_idx phy_idx);
+                               enum rtw89_phy_idx phy_idx)
+{
+       const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
+
+       phy->set_txpwr_offset(rtwdev, chan, phy_idx);
+}
+
 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
                               const struct rtw89_chan *chan,
                               enum rtw89_phy_idx phy_idx);

diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c
index 7b43bcd0952c8f85766d1f0f490438895af5ddb9..8ff875f3fec8b6ce54a8dfc2609968e497d30015 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/phy_be.c
+++ b/drivers/net/wireless/realtek/rtw89/phy_be.c
@@ -174,11 +174,42 @@ static void rtw89_phy_set_txpwr_byrate_be(struct rtw89_dev *rtwdev,
                                                  &addr, phy_idx);
 }
 
+static void rtw89_phy_set_txpwr_offset_be(struct rtw89_dev *rtwdev,
+                                         const struct rtw89_chan *chan,
+                                         enum rtw89_phy_idx phy_idx)
+{
+       struct rtw89_rate_desc desc = {
+               .nss = RTW89_NSS_1,
+               .rs = RTW89_RS_OFFSET,
+       };
+       u8 band = chan->band_type;
+       s8 v[RTW89_RATE_OFFSET_NUM_BE] = {};
+       u32 val;
+
+       rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
+                   "[TXPWR] set txpwr offset on band %d\n", band);
+
+       for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_BE; desc.idx++)
+               v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc);
+
+       val = u32_encode_bits(v[RTW89_RATE_OFFSET_CCK], GENMASK(3, 0)) |
+             u32_encode_bits(v[RTW89_RATE_OFFSET_OFDM], GENMASK(7, 4)) |
+             u32_encode_bits(v[RTW89_RATE_OFFSET_HT], GENMASK(11, 8)) |
+             u32_encode_bits(v[RTW89_RATE_OFFSET_VHT], GENMASK(15, 12)) |
+             u32_encode_bits(v[RTW89_RATE_OFFSET_HE], GENMASK(19, 16)) |
+             u32_encode_bits(v[RTW89_RATE_OFFSET_EHT], GENMASK(23, 20)) |
+             u32_encode_bits(v[RTW89_RATE_OFFSET_DLRU_HE], GENMASK(27, 24)) |
+             u32_encode_bits(v[RTW89_RATE_OFFSET_DLRU_EHT], GENMASK(31, 28));
+
+       rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_BE_PWR_RATE_OFST_CTRL, val);
+}
+
 const struct rtw89_phy_gen_def rtw89_phy_gen_be = {
        .cr_base = 0x20000,
        .ccx = &rtw89_ccx_regs_be,
        .physts = &rtw89_physts_regs_be,
 
        .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_be,
+       .set_txpwr_offset = rtw89_phy_set_txpwr_offset_be,
 };
 EXPORT_SYMBOL(rtw89_phy_gen_be);

diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index 9e40fb28486ee4f9371e48dfba3875b867085ba4..74f757e0076219ce5e940eda108f75826ab21c7c 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -3941,6 +3941,7 @@
 #define R_BE_PWR_MODULE 0x11900
 #define R_BE_PWR_MODULE_C1 0x15900
 
+#define R_BE_PWR_RATE_OFST_CTRL 0x11A30
 #define R_BE_PWR_BY_RATE 0x11E00
 
 #define CMAC1_START_ADDR_BE 0x14000