unspecified, the h/w is not initialized.
 
                pl011,<addr>
+               pl011,mmio32,<addr>
                        Start an early, polled-mode console on a pl011 serial
                        port at the specified address. The pl011 serial port
                        must already be setup and configured. Options are not
-                       yet supported.
+                       yet supported.  If 'mmio32' is specified, then only
+                       the driver will use only 32-bit accessors to read/write
+                       the device registers.
 
                msm_serial,<addr>
                        Start an early, polled-mode console on an msm serial
 
        unsigned int            fifosize;       /* vendor-specific */
        unsigned int            old_cr;         /* state during shutdown */
        bool                    autorts;
-       bool                    access_32b;
        unsigned int            fixed_baud;     /* vendor-set fixed baud rate */
        char                    type[12];
 #ifdef CONFIG_DMA_ENGINE
 {
        void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
 
-       return uap->access_32b ? readl_relaxed(addr) : readw_relaxed(addr);
+       return (uap->port.iotype == UPIO_MEM32) ?
+               readl_relaxed(addr) : readw_relaxed(addr);
 }
 
 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
 {
        void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
 
-       if (uap->access_32b)
+       if (uap->port.iotype == UPIO_MEM32)
                writel_relaxed(val, addr);
        else
                writew_relaxed(val, addr);
 {
        while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
                ;
-       writeb(c, port->membase + UART01x_DR);
+       if (port->iotype == UPIO_MEM32)
+               writel(c, port->membase + UART01x_DR);
+       else
+               writeb(c, port->membase + UART01x_DR);
        while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
                ;
 }
        uap->port.dev = dev;
        uap->port.mapbase = mmiobase->start;
        uap->port.membase = base;
-       uap->port.iotype = UPIO_MEM;
        uap->port.fifosize = uap->fifosize;
        uap->port.flags = UPF_BOOT_AUTOCONF;
        uap->port.line = index;
                return PTR_ERR(uap->clk);
 
        uap->reg_offset = vendor->reg_offset;
-       uap->access_32b = vendor->access_32b;
        uap->vendor = vendor;
        uap->fifosize = vendor->get_fifosize(dev);
+       uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
        uap->port.irq = dev->irq[0];
        uap->port.ops = &amba_pl011_pops;
 
                return -ENOMEM;
 
        uap->reg_offset = vendor_sbsa.reg_offset;
-       uap->access_32b = vendor_sbsa.access_32b;
        uap->vendor     = &vendor_sbsa;
        uap->fifosize   = 32;
+       uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM;
        uap->port.irq   = platform_get_irq(pdev, 0);
        uap->port.ops   = &sbsa_uart_pops;
        uap->fixed_baud = baudrate;