INIT_INI_ARRAY(&ah->iniPcieSerdes,
                           ar9280PciePhy_clkreq_always_on_L1_9280,
                           ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
+#ifdef CONFIG_PM_SLEEP
+               INIT_INI_ARRAY(&ah->iniPcieSerdesWow,
+                              ar9280PciePhy_awow,
+                              ARRAY_SIZE(ar9280PciePhy_awow), 2);
+#endif
 
        if (AR_SREV_9287_11_OR_LATER(ah)) {
                INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 
        {0x00004044, 0x00000000},
 };
 
+static const u32 ar9280PciePhy_awow[][2] = {
+       /* Addr      allmodes  */
+       {0x00004040, 0x9248fd00},
+       {0x00004040, 0x24924924},
+       {0x00004040, 0xa8000019},
+       {0x00004040, 0x13160820},
+       {0x00004040, 0xe5980560},
+       {0x00004040, 0xc01dcffd},
+       {0x00004040, 0x1aaabe41},
+       {0x00004040, 0xbe105554},
+       {0x00004040, 0x00043007},
+       {0x00004044, 0x00000000},
+};
+
 static const u32 ar9285Modes_9285_1_2[][5] = {
        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
        {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
 
        struct ar5416IniArray iniBank7;
        struct ar5416IniArray iniAddac;
        struct ar5416IniArray iniPcieSerdes;
+#ifdef CONFIG_PM_SLEEP
+       struct ar5416IniArray iniPcieSerdesWow;
+#endif
        struct ar5416IniArray iniPcieSerdesLowPower;
        struct ar5416IniArray iniModesFastClock;
        struct ar5416IniArray iniAdditional;