Merge branch 'for-6.15/features' into cxl-for-next

Add CXL Features support. Setup code for enabling in kernel usage of CXL
Features. Expecting EDAC/RAS to utilize CXL Features in kernel for
things such as memory sparing. Also prepartion for enabling of CXL FWCTL
support to issue allowed Features from user space.

diff --cc drivers/cxl/Kconfig
Simple merge

diff --cc drivers/cxl/core/Makefile
index c390f7edc377529aa26cb7ade4cea4ea5d845bd8,b0bfbd9eac9be87af0ceb4c96718c54cd00926b1..086df97a0fcfbc5f74e4ae9130043685a5d66d6a
--- 1/drivers/cxl/core/Makefile
--- 2/drivers/cxl/core/Makefile
+++ b/drivers/cxl/core/Makefile
@@@ -14,8 -14,6 +14,9 @@@ cxl_core-y += pci.
  cxl_core-y += hdm.o
  cxl_core-y += pmu.o
  cxl_core-y += cdat.o
 +cxl_core-y += ras.o
 +cxl_core-y += acpi.o
  cxl_core-$(CONFIG_TRACING) += trace.o
  cxl_core-$(CONFIG_CXL_REGION) += region.o
 +cxl_core-$(CONFIG_CXL_MCE) += mce.o
+ cxl_core-$(CONFIG_CXL_FEATURES) += features.o

diff --cc drivers/cxl/core/core.h
index e35f6e08ddb5bc245fe68a29beded3032c40e76c,17e99a25c29a54724f820d52583f85b4371cc503..15699299dc11d4c8dd83a5fd5db97b58afd594eb
--- 1/drivers/cxl/core/core.h
--- 2/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@@ -115,10 -117,15 +117,21 @@@ bool cxl_need_node_perf_attrs_update(in
  int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port,
                                        struct access_coordinate *c);
  
 +int cxl_ras_init(void);
 +void cxl_ras_exit(void);
 +int cxl_gpf_port_setup(struct device *dport_dev, struct cxl_port *port);
 +int cxl_acpi_get_extended_linear_cache_size(struct resource *backing_res,
 +                                          int nid, resource_size_t *size);
 +
+ #ifdef CONFIG_CXL_FEATURES
+ size_t cxl_get_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid,
+                      enum cxl_get_feat_selection selection,
+                      void *feat_out, size_t feat_out_size, u16 offset,
+                      u16 *return_code);
+ int cxl_set_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid,
+                   u8 feat_version, const void *feat_data,
+                   size_t feat_data_size, u32 feat_flag, u16 offset,
+                   u16 *return_code);
+ #endif
+ 
  #endif /* __CXL_CORE_H__ */

diff --cc drivers/cxl/core/mbox.c
index 7450c4df522e29a8d33f3177a02facb3433cfd76,78c5346e3e891bd591909005a46c5bb826dbe2ac..d72764056ce62afcd462961e050cad59ca90cd8c
--- 1/drivers/cxl/core/mbox.c
--- 2/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@@ -1469,14 -1477,11 +1498,15 @@@ struct cxl_memdev_state *cxl_memdev_sta
        mutex_init(&mds->event.log_lock);
        mds->cxlds.dev = dev;
        mds->cxlds.reg_map.host = dev;
+       mds->cxlds.cxl_mbox.host = dev;
        mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE;
        mds->cxlds.type = CXL_DEVTYPE_CLASSMEM;
 -      mds->ram_perf.qos_class = CXL_QOS_CLASS_INVALID;
 -      mds->pmem_perf.qos_class = CXL_QOS_CLASS_INVALID;
 +
 +      rc = devm_cxl_register_mce_notifier(dev, &mds->mce_notifier);
 +      if (rc == -EOPNOTSUPP)
 +              dev_warn(dev, "CXL MCE unsupported\n");
 +      else if (rc)
 +              return ERR_PTR(rc);
  
        return mds;
  }

diff --cc drivers/cxl/core/memdev.c
index f119309d0c9bee49df73398f1b99fb9d0ce5cb80,2e2e035abdaae01e13d584d8d0b64e7b5a49238d..a16a5886d40a7fe0f47c361255d20eb62d8a4d11
--- 1/drivers/cxl/core/memdev.c
--- 2/drivers/cxl/core/memdev.c
+++ b/drivers/cxl/core/memdev.c
@@@ -580,9 -564,12 +580,11 @@@ EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, "CX
  void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
                                unsigned long *cmds)
  {
 -      down_write(&cxl_memdev_rwsem);
+       struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
+ 
-       bitmap_or(mds->exclusive_cmds, mds->exclusive_cmds, cmds,
-                 CXL_MEM_COMMAND_ID_MAX);
 +      guard(rwsem_write)(&cxl_memdev_rwsem);
 -      up_write(&cxl_memdev_rwsem);
+       bitmap_or(cxl_mbox->exclusive_cmds, cxl_mbox->exclusive_cmds,
+                 cmds, CXL_MEM_COMMAND_ID_MAX);
  }
  EXPORT_SYMBOL_NS_GPL(set_exclusive_cxl_commands, "CXL");
  
@@@ -594,9 -581,12 +596,11 @@@
  void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds,
                                  unsigned long *cmds)
  {
 -      down_write(&cxl_memdev_rwsem);
+       struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
+ 
-       bitmap_andnot(mds->exclusive_cmds, mds->exclusive_cmds, cmds,
-                     CXL_MEM_COMMAND_ID_MAX);
 +      guard(rwsem_write)(&cxl_memdev_rwsem);
 -      up_write(&cxl_memdev_rwsem);
+       bitmap_andnot(cxl_mbox->exclusive_cmds, cxl_mbox->exclusive_cmds,
+                     cmds, CXL_MEM_COMMAND_ID_MAX);
  }
  EXPORT_SYMBOL_NS_GPL(clear_exclusive_cxl_commands, "CXL");
  

diff --cc drivers/cxl/cxlmem.h
index db565d4a9e3c405eaa4ec8d0e1c133527c0cbf74,dd2b7060d501c5462e3de1219e1e11be72b7aef6..3ec6b906371b62a4f93db997b1e088b10ce439a9
--- 1/drivers/cxl/cxlmem.h
--- 2/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@@ -468,20 -408,11 +433,23 @@@ struct cxl_dev_state 
        u64 serial;
        enum cxl_devtype type;
        struct cxl_mailbox cxl_mbox;
+ #ifdef CONFIG_CXL_FEATURES
+       struct cxl_features_state *cxlfs;
+ #endif
  };
  
 +static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
 +{
 +      /*
 +       * Static PMEM may be at partition index 0 when there is no static RAM
 +       * capacity.
 +       */
 +      for (int i = 0; i < cxlds->nr_partitions; i++)
 +              if (cxlds->part[i].mode == CXL_PARTMODE_PMEM)
 +                      return resource_size(&cxlds->part[i].res);
 +      return 0;
 +}
 +
  static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox)
  {
        return dev_get_drvdata(cxl_mbox->host);

diff --cc drivers/cxl/pci.c
Simple merge

diff --cc tools/testing/cxl/Kbuild
index a7ec67d4a0f2bd4b5359f839c3fbbb04e5c37f7d,0a6572ab6f37222692e82f76e2ead609cd777e0a..387f3df8b98851c36aa54478e51ad2a4b5ac4b2f
--- 1/tools/testing/cxl/Kbuild
--- 2/tools/testing/cxl/Kbuild
+++ b/tools/testing/cxl/Kbuild
@@@ -61,11 -61,9 +61,12 @@@ cxl_core-y += $(CXL_CORE_SRC)/pci.
  cxl_core-y += $(CXL_CORE_SRC)/hdm.o
  cxl_core-y += $(CXL_CORE_SRC)/pmu.o
  cxl_core-y += $(CXL_CORE_SRC)/cdat.o
 +cxl_core-y += $(CXL_CORE_SRC)/ras.o
 +cxl_core-y += $(CXL_CORE_SRC)/acpi.o
  cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o
  cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o
 +cxl_core-$(CONFIG_CXL_MCE) += $(CXL_CORE_SRC)/mce.o
+ cxl_core-$(CONFIG_CXL_FEATURES) += $(CXL_CORE_SRC)/features.o
  cxl_core-y += config_check.o
  cxl_core-y += cxl_core_test.o
  cxl_core-y += cxl_core_exports.o

diff --cc tools/testing/cxl/test/mem.c
Simple merge