uint32_t target_vblank, last_flip_vblank;
        bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
        bool pflip_present = false;
-       bool swizzle = true;
        struct {
                struct dc_surface_update surface_updates[MAX_SURFACES];
                struct dc_plane_info plane_infos[MAX_SURFACES];
 
                dc_plane = dm_new_plane_state->dc_state;
 
-               if (dc_plane && !dc_plane->tiling_info.gfx9.swizzle)
-                       swizzle = false;
-
                bundle->surface_updates[planes_count].surface = dc_plane;
                if (new_pcrtc_state->color_mgmt_changed) {
                        bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
                        amdgpu_dm_link_setup_psr(acrtc_state->stream);
                else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
                                                acrtc_state->stream->link->psr_feature_enabled &&
-                                               !acrtc_state->stream->link->psr_allow_active &&
-                                               swizzle) {
+                                               !acrtc_state->stream->link->psr_allow_active) {
                        amdgpu_dm_psr_enable(acrtc_state->stream);
                }