drm/msm/dsi: fix check-before-set in the 7nm dsi_pll code

Fix setting min/max DSI PLL rate for the V4.1 7nm DSI PLL (used on
sm8250). Current code checks for pll->type before it is set (as it is
set in the msm_dsi_pll_init() after calling device-specific functions.

Cc: Jonathan Marek <jonathan@marek.ca>
Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
index a45fe95aff494938f864304fcc8688f40ea3253b..3dc65877fa10daf92dcf25fd79a489a025bd2ac9 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
@@ -163,7 +163,7 @@ struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
                break;
        case MSM_DSI_PHY_7NM:
        case MSM_DSI_PHY_7NM_V4_1:
-               pll = msm_dsi_pll_7nm_init(pdev, id);
+               pll = msm_dsi_pll_7nm_init(pdev, type, id);
                break;
        default:
                pll = ERR_PTR(-ENXIO);

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
index 3405982a092c4653b44b083a7481b1109f2ab9a6..bbecb1de5678e60fab83899b7dbea0acd56c7cc8 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
@@ -117,10 +117,12 @@ msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
 }
 #endif
 #ifdef CONFIG_DRM_MSM_DSI_7NM_PHY
-struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id);
+struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev,
+                                       enum msm_dsi_phy_type type, int id);
 #else
 static inline struct msm_dsi_pll *
-msm_dsi_pll_7nm_init(struct platform_device *pdev, int id)
+msm_dsi_pll_7nm_init(struct platform_device *pdev,
+                                       enum msm_dsi_phy_type type, int id)
 {
        return ERR_PTR(-ENODEV);
 }

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
index 93bf142e4a4e6ad0c4048ce3d2c3f9674f9460c4..c1f6708367ae900cb08898cb21ba1cd6a2e6c794 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
@@ -852,7 +852,8 @@ err_base_clk_hw:
        return ret;
 }
 
-struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id)
+struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev,
+                                       enum msm_dsi_phy_type type, int id)
 {
        struct dsi_pll_7nm *pll_7nm;
        struct msm_dsi_pll *pll;
@@ -885,7 +886,7 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id)
        pll = &pll_7nm->base;
        pll->min_rate = 1000000000UL;
        pll->max_rate = 3500000000UL;
-       if (pll->type == MSM_DSI_PHY_7NM_V4_1) {
+       if (type == MSM_DSI_PHY_7NM_V4_1) {
                pll->min_rate = 600000000UL;
                pll->max_rate = (unsigned long)5000000000ULL;
                /* workaround for max rate overflowing on 32-bit builds: */