drm/i915/pvc: Implement w/a 16016694945

A new PVC-specific workaround has just been added to the BSpec.

BSpec: 64027

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220630201407.16770-1-gustavo.sousa@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 37c1095d8603b42bb5dadc145a2d59bfa74601ea..e6bb24dc7b998c54aae9c1346e7b779c6badc49b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -918,6 +918,10 @@
 #define GEN7_L3CNTLREG1                                _MMIO(0xb01c)
 #define   GEN7_WA_FOR_GEN7_L3_CONTROL          0x3C47FF8C
 #define   GEN7_L3AGDIS                         (1 << 19)
+
+#define XEHPC_LNCFMISCCFGREG0                  _MMIO(0xb01c)
+#define   XEHPC_OVRLSCCC                       REG_BIT(0)
+
 #define GEN7_L3CNTLREG2                                _MMIO(0xb020)
 
 /* MOCS (Memory Object Control State) registers */

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3213c593a55f45a057c70a2a0b756cdc9b8fad9a..dcc1ee392c0d11cf209f1669ffc0f3f7cc720c4b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2687,6 +2687,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
                 * performance guide section.
                 */
                wa_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
+
+               /* Wa_16016694945 */
+               wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
        }
 
        if (IS_XEHPSDV(i915)) {