return ret;
 }
 
+int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
+                             uint16_t level, uint32_t *value)
+{
+       int ret = 0, clk_id = 0;
+       uint32_t param;
+
+       if (!value)
+               return -EINVAL;
+
+       clk_id = smu_clk_get_index(smu, clk_type);
+       if (clk_id < 0)
+               return clk_id;
+
+       param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
+
+       ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
+                                         param);
+       if (ret)
+               return ret;
+
+       ret = smu_read_smc_arg(smu, ¶m);
+       if (ret)
+               return ret;
+
+       /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
+        * now, we un-support it */
+       *value = param & 0x7fffffff;
+
+       return ret;
+}
+
+int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
+                           uint32_t *value)
+{
+       return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
+}
+
 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
                           bool gate)
 {
 
                           enum amd_dpm_forced_level level,
                           enum amd_pp_task task_id);
 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);
+int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
+                             uint16_t level, uint32_t *value);
+int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
+                           uint32_t *value);
 #endif