pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
                "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
                exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
-               _get_rate("sclk_apll"), _get_rate("mout_mpll"),
+               _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
                _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
-               _get_rate("armclk"));
+               _get_rate("arm_clk"));
 }
 
 
 
        samsung_clk_register_gate(exynos5440_gate_clks,
                        ARRAY_SIZE(exynos5440_gate_clks));
 
-       pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("armclk"));
+       pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
        pr_info("exynos5440 clock initialization complete\n");
 }
 CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
 
 unsigned long _get_rate(const char *clk_name)
 {
        struct clk *clk;
-       unsigned long rate;
 
-       clk = clk_get(NULL, clk_name);
-       if (IS_ERR(clk)) {
+       clk = __clk_lookup(clk_name);
+       if (!clk) {
                pr_err("%s: could not find clock %s\n", __func__, clk_name);
                return 0;
        }
-       rate = clk_get_rate(clk);
-       clk_put(clk);
-       return rate;
+
+       return clk_get_rate(clk);
 }