--- /dev/null
+[
+   {
+           "BriefDescription": "ddr cycles event",
+           "EventCode": "0x00",
+           "EventName": "imx8mq_ddr.cycles",
+           "Unit": "imx8_ddr",
+           "Compat": "i.MX8MQ"
+   },
+   {
+           "BriefDescription": "ddr read-cycles event",
+           "EventCode": "0x2a",
+           "EventName": "imx8mq_ddr.read_cycles",
+           "Unit": "imx8_ddr",
+           "Compat": "i.MX8MQ"
+   },
+   {
+           "BriefDescription": "ddr write-cycles event",
+           "EventCode": "0x2b",
+           "EventName": "imx8mq_ddr.write_cycles",
+           "Unit": "imx8_ddr",
+           "Compat": "i.MX8MQ"
+   },
+   {
+           "BriefDescription": "ddr read event",
+           "EventCode": "0x35",
+           "EventName": "imx8mq_ddr.read",
+           "Unit": "imx8_ddr",
+           "Compat": "i.MX8MQ"
+   },
+   {
+           "BriefDescription": "ddr write event",
+           "EventCode": "0x38",
+           "EventName": "imx8mq_ddr.write",
+           "Unit": "imx8_ddr",
+           "Compat": "i.MX8MQ"
+   }
+]
 
--- /dev/null
+[
+   {
+           "BriefDescription": "bytes all masters read from ddr based on read-cycles event",
+           "MetricName": "imx8mq_ddr_read.all",
+           "MetricExpr": "imx8mq_ddr.read_cycles * 4 * 4",
+           "ScaleUnit": "9.765625e-4KB",
+           "Unit": "imx8_ddr",
+           "Compat": "i.MX8MQ"
+   },
+   {
+           "BriefDescription": "bytes all masters write to ddr based on write-cycles event",
+           "MetricName": "imx8mq_ddr_write.all",
+           "MetricExpr": "imx8mq_ddr.write_cycles * 4 * 4",
+           "ScaleUnit": "9.765625e-4KB",
+           "Unit": "imx8_ddr",
+           "Compat": "i.MX8MQ"
+    }
+]