adev->doorbell_index.last_non_cp;
                }
 
-               kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
+               kgd2kfd_device_init(adev->kfd.dev, adev->ddev, &gpu_resources);
        }
 }
 
 
                              const struct kfd2kgd_calls *f2g,
                              unsigned int asic_type, bool vf);
 bool kgd2kfd_device_init(struct kfd_dev *kfd,
+                        struct drm_device *ddev,
                         const struct kgd2kfd_shared_resources *gpu_resources);
 void kgd2kfd_device_exit(struct kfd_dev *kfd);
 void kgd2kfd_suspend(struct kfd_dev *kfd);
 
 }
 
 bool kgd2kfd_device_init(struct kfd_dev *kfd,
+                        struct drm_device *ddev,
                         const struct kgd2kfd_shared_resources *gpu_resources)
 {
        unsigned int size;
 
+       kfd->ddev = ddev;
        kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
                        KGD_ENGINE_MEC1);
        kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
 
 /* GPU ID hash width in bits */
 #define KFD_GPU_ID_HASH_WIDTH 16
 
+struct drm_device;
+
 /* Use upper bits of mmap offset to store KFD driver specific information.
  * BITS[63:62] - Encode MMAP type
  * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to
 
        const struct kfd_device_info *device_info;
        struct pci_dev *pdev;
+       struct drm_device *ddev;
 
        unsigned int id;                /* topology stub index */