interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTA>;
resets = <&bpmp TEGRA186_RESET_UARTA>;
+ dmas = <&gpcdma 8>, <&gpcdma 8>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTB>;
resets = <&bpmp TEGRA186_RESET_UARTB>;
+ dmas = <&gpcdma 9>, <&gpcdma 9>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTD>;
resets = <&bpmp TEGRA186_RESET_UARTD>;
+ dmas = <&gpcdma 19>, <&gpcdma 19>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTE>;
resets = <&bpmp TEGRA186_RESET_UARTE>;
+ dmas = <&gpcdma 20>, <&gpcdma 20>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTF>;
resets = <&bpmp TEGRA186_RESET_UARTF>;
+ dmas = <&gpcdma 12>, <&gpcdma 12>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTC>;
resets = <&bpmp TEGRA186_RESET_UARTC>;
+ dmas = <&gpcdma 3>, <&gpcdma 3>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTG>;
resets = <&bpmp TEGRA186_RESET_UARTG>;
+ dmas = <&gpcdma 2>, <&gpcdma 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTA>;
resets = <&bpmp TEGRA194_RESET_UARTA>;
+ dmas = <&gpcdma 8>, <&gpcdma 8>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTB>;
resets = <&bpmp TEGRA194_RESET_UARTB>;
+ dmas = <&gpcdma 9>, <&gpcdma 9>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTD>;
resets = <&bpmp TEGRA194_RESET_UARTD>;
+ dmas = <&gpcdma 19>, <&gpcdma 19>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTE>;
resets = <&bpmp TEGRA194_RESET_UARTE>;
+ dmas = <&gpcdma 20>, <&gpcdma 20>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTF>;
resets = <&bpmp TEGRA194_RESET_UARTF>;
+ dmas = <&gpcdma 12>, <&gpcdma 12>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTH>;
resets = <&bpmp TEGRA194_RESET_UARTH>;
+ dmas = <&gpcdma 13>, <&gpcdma 13>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTC>;
resets = <&bpmp TEGRA194_RESET_UARTC>;
+ dmas = <&gpcdma 3>, <&gpcdma 3>;
+ dma-names = "rx", "tx";
status = "disabled";
};
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_UARTG>;
resets = <&bpmp TEGRA194_RESET_UARTG>;
+ dmas = <&gpcdma 2>, <&gpcdma 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};