arm: zynq: dt: Set correct L2 ram latencies

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 6f54a64850eb0fef446fd13390f019d5ab277cdb..e32b92b949d2fe762d52ed40e315421786b16113 100644 (file)
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -41,8 +41,8 @@
                L2: cache-controller {
                        compatible = "arm,pl310-cache";
                        reg = <0xF8F02000 0x1000>;
-                       arm,data-latency = <2 3 2>;
-                       arm,tag-latency = <2 3 2>;
+                       arm,data-latency = <3 2 2>;
+                       arm,tag-latency = <2 2 2>;
                        cache-unified;
                        cache-level = <2>;
                };