drm/i915: Fix the SCC/SSC typo in the SPLL bits definition

We're talking about Spread Spectrum Clocks here, thus SSC.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c8c8dd0ff7b49e0b2d8923817c78824c031349fb..8200c317f1fd74287eda0d6a878ede39f3def391 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4496,8 +4496,8 @@
 /* SPLL */
 #define SPLL_CTL                       0x46020
 #define  SPLL_PLL_ENABLE               (1<<31)
-#define  SPLL_PLL_SCC                  (1<<28)
-#define  SPLL_PLL_NON_SCC              (2<<28)
+#define  SPLL_PLL_SSC                  (1<<28)
+#define  SPLL_PLL_NON_SSC              (2<<28)
 #define  SPLL_PLL_FREQ_810MHz          (0<<26)
 #define  SPLL_PLL_FREQ_1350MHz         (1<<26)
 
@@ -4506,7 +4506,7 @@
 #define WRPLL_CTL2                     0x46060
 #define  WRPLL_PLL_ENABLE              (1<<31)
 #define  WRPLL_PLL_SELECT_SSC          (0x01<<28)
-#define  WRPLL_PLL_SELECT_NON_SCC      (0x02<<28)
+#define  WRPLL_PLL_SELECT_NON_SSC      (0x02<<28)
 #define  WRPLL_PLL_SELECT_LCPLL_2700   (0x03<<28)
 /* WRPLL divider programming */
 #define  WRPLL_DIVIDER_REFERENCE(x)    ((x)<<0)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e79d0db4abf502b4d1cfb0201538c0aa9d44bdd7..a78860a04a5664ccd51c9e8a7936278089344234 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -814,7 +814,7 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
                WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
                     "SPLL already enabled\n");
 
-               val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SCC;
+               val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
 
        } else {
                WARN(1, "Invalid DDI encoder type %d\n", type);