phy: qcom-qmp: pcs-usb: Add v6 register offsets

The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB.
Add the new PCS USB specific offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230208183421.2874423-5-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 9982269b2cd9653dc574161ee7a3a5dd2f4d8254..25579bba0427922f16dd4443145919ae60d5bad3 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -26,6 +26,7 @@
 #include "phy-qcom-qmp-pcs-misc-v3.h"
 #include "phy-qcom-qmp-pcs-usb-v4.h"
 #include "phy-qcom-qmp-pcs-usb-v5.h"
+#include "phy-qcom-qmp-pcs-usb-v6.h"
 
 /* QPHY_SW_RESET bit */
 #define SW_RESET                               BIT(0)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
new file mode 100644 (file)
index 0000000..9510e63
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_USB_V6_H_
+#define QCOM_PHY_QMP_PCS_USB_V6_H_
+
+/* Only for QMP V6 PHY - USB3 have different offsets than V5 */
+#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1            0xc4
+#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2            0xc8
+#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3            0xcc
+#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6            0xd8
+#define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1             0xdc
+#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1       0x90
+#define QPHY_USB_V6_PCS_RX_SIGDET_LVL                  0x188
+#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L           0x190
+#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H           0x194
+#define QPHY_USB_V6_PCS_CDR_RESET_TIME                 0x1b0
+#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1           0x1c0
+#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2           0x1c4
+#define QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG               0x1d0
+#define QPHY_USB_V6_PCS_EQ_CONFIG1                     0x1dc
+#define QPHY_USB_V6_PCS_EQ_CONFIG5                     0x1ec
+
+#define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL   0x18
+#define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2  0x3c
+#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L                0x40
+#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H                0x44
+
+#endif