That function never fails, drop the error return.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 
        if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready ||
            !down_read_trylock(&adev->reset_domain->sem)) {
-               return adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
-                                                               flush_type,
-                                                               all_hub, inst);
+               adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
+                                                        flush_type, all_hub,
+                                                        inst);
+               return 0;
        }
 
        /* 2 dwords flush + 8 dwords fence */
 
        void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
                                uint32_t vmhub, uint32_t flush_type);
        /* flush the vm tlb via pasid */
-       int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
-                                       uint32_t flush_type, bool all_hub,
-                                       uint32_t inst);
+       void (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
+                                   uint32_t flush_type, bool all_hub,
+                                   uint32_t inst);
        /* flush the vm tlb via ring */
        uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
                                       uint64_t pd_addr);
 
  *
  * Flush the TLB for the requested pasid.
  */
-static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
-                                       uint16_t pasid, uint32_t flush_type,
-                                       bool all_hub, uint32_t inst)
+static void gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+                                         uint16_t pasid, uint32_t flush_type,
+                                         bool all_hub, uint32_t inst)
 {
        uint16_t queried;
        int vmid, i;
                                                flush_type);
                }
        }
-       return 0;
 }
 
 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 
  *
  * Flush the TLB for the requested pasid.
  */
-static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
-                                       uint16_t pasid, uint32_t flush_type,
-                                       bool all_hub, uint32_t inst)
+static void gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+                                         uint16_t pasid, uint32_t flush_type,
+                                         bool all_hub, uint32_t inst)
 {
        uint16_t queried;
        int vmid, i;
                                                flush_type);
                }
        }
-       return 0;
 }
 
 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 
  *
  * Flush the TLB for the requested pasid.
  */
-static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
-                                       uint16_t pasid, uint32_t flush_type,
-                                       bool all_hub, uint32_t inst)
+static void gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+                                        uint16_t pasid, uint32_t flush_type,
+                                        bool all_hub, uint32_t inst)
 {
        u32 mask = 0x0;
        int vmid;
 
        if (!down_read_trylock(&adev->reset_domain->sem))
-               return 0;
+               return;
 
        for (vmid = 1; vmid < 16; vmid++) {
                u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
        WREG32(mmVM_INVALIDATE_REQUEST, mask);
        RREG32(mmVM_INVALIDATE_RESPONSE);
        up_read(&adev->reset_domain->sem);
-       return 0;
 }
 
 /*
 
  *
  * Flush the TLB for the requested pasid.
  */
-static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
-                                       uint16_t pasid, uint32_t flush_type,
-                                       bool all_hub, uint32_t inst)
+static void gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+                                        uint16_t pasid, uint32_t flush_type,
+                                        bool all_hub, uint32_t inst)
 {
        u32 mask = 0x0;
        int vmid;
 
        if (!down_read_trylock(&adev->reset_domain->sem))
-               return 0;
+               return;
 
        for (vmid = 1; vmid < 16; vmid++) {
                u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
        WREG32(mmVM_INVALIDATE_REQUEST, mask);
        RREG32(mmVM_INVALIDATE_RESPONSE);
        up_read(&adev->reset_domain->sem);
-       return 0;
 }
 
 /*
 
  *
  * Flush the TLB for the requested pasid.
  */
-static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
-                                       uint16_t pasid, uint32_t flush_type,
-                                       bool all_hub, uint32_t inst)
+static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+                                        uint16_t pasid, uint32_t flush_type,
+                                        bool all_hub, uint32_t inst)
 {
        uint16_t queried;
        int i, vmid;
                                               flush_type);
                }
        }
-
-       return 0;
 }
 
 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,